Specification Sheet

Thermal Management
92 Datasheet, Volume 1 of 2
5.3 S-Processor Line Thermal and Power
Specifications
Table 5-2. TDP Specifications (S-Processor Line)
Segment
and
Package
Processor IA
Cores,
Graphics
Configuration
and TDP
Configuration
Processor IA
Core
Frequency
Graphics core
Frequency
Thermal
Design Power
(TDP) [w]
Notes
S-
Processor
Line LGA
Hexa Core GT2
95W
Base 3.2 GHz to 3.7
GHz
1.0 GHz to 1.2
GHz
95
1,9,10,
11,12,
15
LPM 0.8 GHz 0.35 GHz N/A
Quad Core GT2
95W
Base 4.0 GHz 1.15 GHz 95 1,9,10,
11,12,
15
LPM
0.8 GHz 0.35 GHz N/A
Hexa Core GT2
65W
Base 2.8 GHz to 3.3
GHz
1.0 GHz to 1.2
GHz
65
1,9,10,
11,12,
15
LPM 0.8 GHz 0.35 GHz N/A
Quad Core GT2
65W
Base 3.6 GHz 1.1 GHz 65 1,9,10,
11,12,
15
LPM
0.8 GHz 0.35 GHz N/A
Table 5-3. Low Power and TTV Specifications (S-Processor Line)
Processor IA Cores,
Graphics
Configuration and TDP
PCG
7
Max Power
Package C7
(W)
1,4,5
Max Power
Package C8
(W)
1,4,5
TTV TDP
(W)
6,7
Min
T
CASE
(°C)
Max TTV
T
CASE
(°C)
Hexa Core GT2 95W 2015D N/A N/A 95 0 64.5
Hexa Core GT2 65W 2015C N/A N/A 65 0 71.4
Quad Core GT2 62W 2015C N/A N/A 62 0 69.9
Notes:
1. The package C-state power is the worst case power in the system configured as follows:
a. Memory configured for DDR4 2400 and populated with two DIMMs per channel.
b. DMI and PCIe links are at L1
2. Specification at DTS = 50 °C and minimum voltage loadline.
3. Specification at DTS = 35 °C and minimum voltage loadline.
4. These DTS values in Notes 2 - 3 are based on the TCC Activation MSR having a value of 100, see Section
5.1.5, “Thermal Management Features”.
5. These values are specified at V
CC_MAX and VNOM for all other voltage rails for all processor frequencies.
Systems should be designed to ensure the processor is not to be subjected to any static V
CC and ICC
combination wherein VCCP exceeds VCCP_MAX at specified ICCP. See the loadline specifications.
6. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at DTS = -1.TDP is achieved with the
Memory configured for DDR4 2400 and 2 DIMMs per channel.
7. Platform Compatibility Guide (PCG) (previously known as FMB) provides a design target for meeting all
planned processor frequency requirements.
8. Not 100% tested. Specified by design characterization.
Table 5-4. T
CONTROL
Offset Configuration (S-Processor Line - Client) (Sheet 1 of 2)
Segment Hexa Core GT2 Quad Core GT2
TDP [W] 95 65 35 62 35
TEMP_TARGET (T
CONTROL
) [ºC] 18 18 6 20 7