Specification Sheet

8 Datasheet, Volume 1 of 2
2-24 Supported Resolutions1 for HBR2 (5.4 Gbps) by Link Width.........................................45
4-1 System States........................................................................................................63
4-2 Processor IA Core / Package State Support ................................................................64
4-3 Integrated Memory Controller (IMC) States ................................................................64
4-4 PCI Express* Link States .........................................................................................64
4-5 Direct Media Interface (DMI) States ..........................................................................64
4-6 G, S, and C Interface State Combinations ..................................................................65
4-7 Deepest Package C-State Available ...........................................................................72
4-8 Targeted Memory State Conditions............................................................................74
4-9 Package C-States with PCIe* Link States Dependencies ...............................................76
5-1 Configurable TDP Modes ..........................................................................................83
5-2 TDP Specifications (S-Processor Line) ........................................................................92
5-3 Low Power and TTV Specifications (S-Processor Line) ..................................................92
5-4 T
CONTROL
Offset Configuration (S-Processor Line - Client) .............................................92
5-5 Thermal Test Vehicle Thermal Profile for PCG 2015D Processor .....................................93
5-6 Thermal Test Vehicle Thermal Profile for PCG 2015C Processor .....................................94
5-7 Thermal Test Vehicle Thermal Profile for PCG 2015B Processor .....................................95
5-8 Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above T
CONTROL
............98
5-9 Thermal Margin Slope .............................................................................................99
6-1 Signal Tables Terminology ..................................................................................... 100
6-2 DDR4 Memory Interface ........................................................................................100
6-3 System Memory Reference and Compensation Signals ...............................................102
6-4 PCI Express* Interface .......................................................................................... 102
6-5 DMI Interface Signals............................................................................................102
6-6 Reset and Miscellaneous Signals ............................................................................. 103
6-7 embedded DisplayPort* Signals .............................................................................. 103
6-8 Display Interface Signals ....................................................................................... 104
6-9 Processor Clocking Signals .....................................................................................104
6-10 Testability Signals................................................................................................. 105
6-11 Error and Thermal Protection Signals....................................................................... 105
6-12 Power Sequencing Signals ..................................................................................... 106
6-13 Processor Power Rails Signals.................................................................................107
6-14 GND, RSVD, and NCTF Signals ............................................................................... 108
6-15 Processor Internal Pull-Up / Pull-Down Terminations.................................................. 108
7-1 Processor Power Rails............................................................................................ 109
7-2 Processor IA core (Vcc) Active and Idle Mode DC Voltage and Current Specifications...... 110
7-3 Processor Graphics (Vcc
GT
) Supply DC Voltage and Current Specifications ....................111
7-4 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications .................... 112
7-5 System Agent (VccSA) Supply DC Voltage and Current Specifications .......................... 113
7-6 Processor I/O (Vcc
IO
) Supply DC Voltage and Current Specifications ............................ 113
7-7 Vcc Sustain (VccST) Supply DC Voltage and Current Specifications.............................. 114
7-8 Processor PLL (VccPLL) Supply DC Voltage and Current Specifications.......................... 114
7-9 Processor PLL_OC (VccPLL_OC) Supply DC Voltage and Current Specifications ..............115
7-10 DDR4 Signal Group DC Specifications ......................................................................115
7-11 PCI Express* Graphics (PEG) Group DC Specifications ...............................................116
7-12 Digital Display Interface Group DC Specifications (DP/HDMI) ...................................... 116
7-13 embedded DisplayPort* (eDP*) Group DC Specifications ............................................117
7-14 CMOS Signal Group DC Specifications...................................................................... 117
7-15 GTL Signal Group and Open Drain Signal Group DC Specifications ............................... 117
7-16 PECI DC Electrical Limits........................................................................................ 118
8-1 Package Mechanical Attributes................................................................................120
8-2 Package Storage Specifications...............................................................................120
9-1 Ball Listing........................................................................................................... 125