Specification Sheet

Power Management
74 Datasheet, Volume 1 of 2
Selection of power modes should be according to power-performance or thermal trade-
off of a given system:
• When trying to achieve maximum performance and power or thermal consideration
is not an issue: use no power-down
• In a system which tries to minimize power-consumption, try using the deepest
power-down mode possible – PPD/DLL-off with a low idle timer value
• In high-performance systems with dense packaging (that is, tricky thermal design)
the power-down mode should be considered in order to reduce the heating and
avoid DDR throttling caused by the heating.
The default value that BIOS configures in PM PDWN configuration register is 6080 –
that is, PPD/DLL-off mode with idle timer of 0x80, or 128 DCLKs. This is a balanced
setting with deep power-down mode and moderate idle timer value.
The idle timer expiration count defines the # of DCLKs that a rank is idle that causes
entry to the selected power mode. As this timer is set to a shorter time the IMC will
have more opportunities to put the DDR in power-down. There is no BIOS hook to set
this register. Customers choosing to change the value of this register can do it by
changing it in the BIOS. For experiments, this register can be modified in real time if
BIOS does not lock the IMC registers.
4.3.2.1 Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the reset pin) once power is applied. It should be driven LOW by the DDR
controller to make sure the SDRAM components float DQ and DQS during power-up.
CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
4.3.2.2 Conditional Self-Refresh
During S0 idle state, system memory may be conditionally placed into self-refresh state
when the processor is in package C3 or deeper power state. Refer to Section 4.6.1.1 for
more details on conditional self-refresh with Intel HD Graphics enabled.
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh, the
processor IA core flushes pending cycles and then enters SDRAM ranks that are not
used by the processor graphics into self-refresh. The CKE signals remain LOW so the
SDRAM devices perform self-refresh.
The target behavior is to enter self-refresh for package C3 or deeper power states as
long as there are no memory requests to service.
Table 4-8. Targeted Memory State Conditions (Sheet 1 of 2)
State Memory State with Processor Graphics Memory State with External Graphics
C0, C1, C1E
Dynamic memory rank power-down based on
idle conditions.
Dynamic memory rank power-down based on
idle conditions.
C3, C6, C7 or
deeper
If the processor graphics engine is idle and
there are no pending display requests, then
enter self-refresh. Otherwise use dynamic
memory rank power-down based on idle
conditions.
If there are no memory requests, then enter
self-refresh. Otherwise use dynamic memory
rank power-down based on idle conditions.