Specification Sheet

Datasheet, Volume 1 of 2 7
2-2 Interleave (IL) and Non-Interleave (NIL) Modes Mapping............................................. 24
2-3 PCI Express* Related Register Structures in the Processor ........................................... 27
2-4 Example for DMI Lane Reversal Connection ............................................................... 29
2-5 Video Analytics Common Use Cases .......................................................................... 34
2-6 Gen 9 LP Block Diagram.......................................................................................... 35
2-7 Processor Display Architecture (with 3 DDI ports as an example) .................................. 39
2-8 DisplayPort* Overview ............................................................................................ 40
2-9 HDMI* Overview .................................................................................................... 41
2-10 Example for PECI Host-Clients Connection ................................................................. 46
2-11 Example for PECI EC Connection ............................................................................. 47
3-1 Device to Domain Mapping Structures ....................................................................... 51
4-1 Processor Power States........................................................................................... 62
4-2 Processor Package and IA Core C-States ................................................................... 63
4-3 Idle Power Management Breakdown of the Processor IA Cores ..................................... 66
4-4 Package C-State Entry and Exit................................................................................ 70
5-1 Package Power Control............................................................................................ 82
5-2 Thermal Test Vehicle Thermal Profile for PCG 2015D Processor..................................... 93
5-3 Thermal Test Vehicle Thermal Profile for PCG 2015C Processor ..................................... 94
5-4 Thermal Test Vehicle Thermal Profile for PCG 2015B Processor ..................................... 95
5-5 Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location .............. 97
5-6 Digital Thermal Sensor (DTS) 1.1 Definition Points...................................................... 98
5-7 Digital Thermal Sensor (DTS) 2.0 Definition Points...................................................... 99
7-1 Input Device Hysteresis ........................................................................................ 119
9-1 Ball Map Left (40-27)............................................................................................ 122
9-2 Ball Map Center (26-13)........................................................................................ 123
9-3 Ball Map Right (12-1) ........................................................................................... 124
Tables
1-1 Processor Lines ...................................................................................................... 10
1-2 Terminology .......................................................................................................... 14
1-3 Related Documents ................................................................................................ 16
2-1 Processor DDR Memory Speed Support ..................................................................... 18
2-2 Supported DDR4 Non-ECC UDIMM Module Configurations ............................................ 19
2-3 Supported DDR4 Non-ECC SODIMM Module Configurations .......................................... 19
2-4 DRAM System Memory Timing Support ..................................................................... 20
2-5 Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping........................................ 23
2-6 PCI Express* Bifurcation and Lane Reversal Mapping .................................................. 25
2-7 PCI Express* Maximum Transfer Rates and Theoretical Bandwidth................................ 26
2-8 Hardware Accelerated Video Decoding....................................................................... 31
2-9 Hardware Accelerated Video Encode ......................................................................... 32
2-10 Switchable/Hybrid Graphics Support ......................................................................... 33
2-11 GT2 Graphics Frequency (S-Processor Line) ............................................................... 35
2-12 DDI Ports Availability .............................................................................................. 36
2-13 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary..................................... 37
2-14 Display Technologies Support .................................................................................. 37
2-15 Display Resolutions and Link Bandwidth for Multi-Stream Transport calculations ............. 37
2-16 Processor Supported Audio Formats over HDMI and DisplayPort*.................................. 42
2-17 Maximum Display Resolution .................................................................................. 42
2-18 S -Processor Line Display Resolution Configuration .................................................... 43
2-19 HDCP Display supported Implications Table ............................................................... 43
2-20 Display Link Data Rate Support ................................................................................ 44
2-21 Display Resolution and Link Rate Support .................................................................. 44
2-22 Display Bit Per Pixel (BPP) Support .......................................................................... 45
2-23 Supported Resolutions1 for HBR (2.7 Gbps) by Link Width .......................................... 45