Specification Sheet

Datasheet, Volume 1 of 2 39
Interfaces
• For display resolutions driving capability see Table 2-17, “Maximum Display
Resolution”.
• DisplayPort* Aux CH supported by the processor, while DDC channel, Panel power
sequencing, and HPD are supported through the PCH.
Display is the presentation stage of graphics. This involves:
• Pulling rendered data from memory
• Converting raw data into pixels
• Blending surfaces into a frame
• Organizing pixels into frames
• Optionally scaling the image to the desired size
• Re-timing data for the intended target
• Formatting data according to the port output standard
Figure 2-7. Processor Display Architecture (with 3 DDI ports as an example)
Display
PipeA
Display
PipeB
Display
PipeC
TranscoderA
DP/HDMI/DVI
Timing,VDIP
TranscoderB
DP/HDMI/DVI
Timing,VDIP
TranscoderC
DP/HDMI/DVI
Timing,VDIP
Audio
Codec
eDP
Mux
Transcoder
eDP
DPencoder
DPTiming,
VDIP
DPT,SRID
X2eDP
X4DDIC
X4DDID
eDP
eDP
AUX
X3DP’s
AUX
X4DDIB
Memory
Interface
Ports
Mux
DDI
ports:
B,C,D
X2DDIE
Interrupt
Backlight
modulation
PCH
HPD
MUX
Processor
x4eDP
Or
x2eDP+x2DP
DDIB
(X4DP/HDMI/DVI)
DDIC
(X4DP/HDMI/DVI)
DDID
(X4DP/HDMI/DVI)