Specification Sheet

Datasheet, Volume 1 of 2 37
Interfaces
2.5.2 eDP* Bifurcation
2.5.3 Display Technologies
• The HDMI* interface supports HDMI with 3D, 4Kx2K @ 24 Hz, Deep Color, and
x.v.Color.
• The processor supports High-bandwidth Digital Content Protection (HDCP) for high
definition content playback over digital interfaces. HDCP is not supported for eDP.
• The processor supports eDP display authentication: Alternate Scrambler Seed
Reset (ASSR).
• The processor supports Multi-Stream Transport (MST), enabling multiple monitors
to be used via a single DisplayPort connector.
The maximum MST DP supported resolution for S-Processors is shown in the following
table.
Table 2-13. VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary
Port S-Processor Line
eDP - DDIA
(eDP lower x2 lanes, [1:0])
Yes
VGA - DDIE
2
(DP upper x2 lanes, [3:2])
Yes
1
Notes:
1. Requires a DP to VGA converter.
2. DP-to-VGA converter on the processor ports is supported using external dongle only, display
driver software for VGA dongles which configures the VGA port as a DP branch device.
3. For example, DT SKUs can use eDP_AUX for VGA converter which is available as free Design
but HPD should be used as DDPE_HPD3.
Table 2-14. Display Technologies Support
Technology Standard
eDP* 1.4 VESA* Embedded DisplayPort* Standard 1.4
DisplayPort* 1.2
VESA DisplayPort* Standard 1.2
VESA DisplayPort* PHY Compliance Test Specification 1.2
VESA DisplayPort* Link Layer Compliance Test Specification 1.2
HDMI* 1.4
1
High-Definition Multimedia Interface Specification Version 1.4
Notes:
1. HDMI* 2.0/2.0a support is possible using LS-Pcon converter chip connected to the DP port. The LS-Pcon
supports 2 modes:
a. Level shifter for HDMI 1.4 resolutions.
b. DP-HDMI 2.0 protocol converter for HDMI 2.0 resolutions.
Table 2-15. Display Resolutions and Link Bandwidth for Multi-Stream Transport
calculations (Sheet 1 of 2)
Pixels per line Lines
Refresh
Rate [Hz]
Pixel Clock
[MHz]
Link Bandwidth
[Gbps]
640 480 60 25.2 0.76
800 600 60 40 1.20
1024 768 60 65 1.95