Specification Sheet

Datasheet, Volume 1 of 2 35
Interfaces
2.4.6 Gen 9 LP (9th Generation Low Power) Block Diagram
2.4.7 GT2 Graphic Frequency
Figure 2-6. Gen 9 LP Block Diagram
Table 2-11. GT2 Graphics Frequency (S-Processor Line)
Segment GT Unslice
GT Unslice +
1 GT Slice
GT Unslice +
2 GT Slice
S-Processor Line - Hexa Core
with GT2
GT Max Dynamic frequency
[GT Unslice only] -
(1or2)BIN
—
Cache/Memory Interface
3D Pipeline
General Purpose Pipeline
State ManagementScheduler
Power Management
LLC
System Memory
Video
Decode
Video
Encode
Video
Decode
Video
Encode
eDRAM
L3 Cache
EU Array
Local Thread Dispatch
Setup, Rasterization, Z Complex, Color
Global Thread Dispatch
Local Memory
Load/Store/Scatter/Gather
Sampler
EU Array
Local Memory
Load/Store/Scatter/Gather
Sampler
EU
EU
EU EU
EU
EU
L3 Cache
EU Array
Local Thread Dispatch
Setup, Rasterization, Z Complex, Color
Local Memory
Load/Store/Scatter/Gather
Sampler
EU Array
Local Memory
Load/Store/Scatter/Gather
Sampler
EU
EU
EU EU
EU
EU
EU
EU
EU EU
EU
EU
EU
EU
EU EU
EU
EU