Specification Sheet

Interfaces

18 Datasheet, Volume 1 of 2

2 Interfaces

2.1 System Memory Interface

• Two channels of DDR4 memory with a maximum of two DIMMs per channel. DDR

technologies, number of DIMMs per channel, number of ranks per channel are SKU

dependent.

• UDIMM, SO-DIMM, and Memory Down support (based on SKU)

• Single-channel and dual-channel memory organization modes

• Data burst length of eight for all memory organization modes

• DDR4 I/O Voltage of 1.2V

• 64-bit wide channels

• Non-ECC UDIMM and SODIMM DDR4 support (based on SKU)

• Theoretical maximum memory bandwidth of:

— 29.1 GB/s in dual-channel mode assuming 1866 MT/s

— 33.3 GB/s in dual-channel mode assuming 2133 MT/s

— 37.5 GB/s in dual-channel mode assuming 2400 MT/s

— 41.6 GB/s in dual-channel mode assuming 2666 MT/s

Note: Memory down of all technologies (DDR4) should be implemented homogeneously,

which means that all DRAM devices should be from the same vendor and have the

same part number. Implementing a mix of DRAM devices may cause serious signal

integrity and functional issues.

Note: If the S-Processor Line’s memory interface is configured to one DIMM per Channel, the

processor can use either of the DIMMs, DIMM0 or DIMM1, signals CTRL[1:0] or

CTRL[3:2].

2.1.1 System Memory Technology Supported

The Integrated Memory Controller (IMC) supports DDR4 protocols with two

independent, 64-bit wide channels.

Table 2-1. Processor DDR Memory Speed Support (Sheet 1 of 2)

Processor Line DDR4 1DPC [MT/s] DDR4 2DPC [MT/s] LPDDR3 [MT/s]

S-Processor Line

(AIO SODIMM)

2400

2133

N/A

S-Processor Line

(DT UDIMM) 6+2

2666 2666

N/A

S-Processor Line

(DT UDIMM) 4+2

2400 2400 N/A