Specification Sheet
Datasheet, Volume 1 of 2 115
Electrical Specifications
7.2.2 Processor Interfaces DC Specifications
7.2.2.1 DDR4 DC Specifications
Table 7-9. Processor PLL_OC (Vcc
PLL_OC
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max
Un
it
Notes
1,2
Vcc
PLL_OC
PLL_OC supply
voltage (DC + AC
specification)
All
—V
DDQ
—V 3
TOB
CCPLL_OC
Vcc
PLL_OC
Tolerance All AC+DC:± 5 % 3,4
Icc
MAX_VCCPLL_OC
Max Current for
Vcc
PLL_OC
Rail
S-Processor Line - Quad Core GT2
S-Processor Line - Hexa Core GT2
——
130
130
mA
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured on package pins as near as possible to the processor with an
oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the
oscilloscope probe.
4. For Voltage less than 1V, TOB will be 50 mV.
Table 7-10. DDR4 Signal Group DC Specifications (Sheet 1 of 2)
Symbol Parameter
US-Processor Line
Units Notes
1
Min Typ Max
V
IL
Input Low Voltage
— —
VREF(INT) -
0.07*VDDQ
V
2, 4, 8,
9, 13
V
IH
Input High Voltage VREF(INT)
+
0.07*VDDQ
— — V
3, 4, 8,
9, 13
R
ON_UP/DN(DQ)
DDR4 Data Buffer pull-up/ down Resistance Trainable 11
R
ODT(DQ)
DDR4 On-die termination equivalent
resistance for data signals
Train abl e 11
V
ODT(DC)
DDR4 On-die termination DC working point
(driver set to receive mode)
0.45*V
DDQ
0.5*V
DDQ
0.55*V
DDQ
V 9
R
ON_UP/DN(CK)
DDR4 Clock Buffer pull-up/ down Resistance 0.8*Typ 26 1.2*Typ 5, 11
R
ON_UP/DN(CMD)
DDR4 Command Buffer pull-up/ down
Resistance
0.8*Typ 20 1.2*Typ 11
R
ON_UP/DN(CTL)
DDR4 Control Buffer pull-up/ down Resistance 0.8*Typ 20 1.2*Typ 5, 11
R
ON_UP/DN
(DDR_VTT_CNTL)
System Memory Power Gate Control Buffer
Pull-Up/ down Resistance
40 — 140 -
I
LI
Input Leakage Current (DQ, CK)
0 V
0.2*V
DDQ
0.8*V
DDQ
— — 1 mA -
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VREF_CA
VREF output voltage
V
DDQ
/2-0.06 V
DDQ
/2 V
DDQ
/2+0.06 V
12,14,
15