Specification Sheet

Electrical Specifications
114 Datasheet, Volume 1 of 2
7.2.1.6 Vcc
ST
DC Specifications
7.2.1.7 Vcc
PLL
DC Specifications
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured across Vcc
IO
_
SENSE
and Vss
IO
_
SENSE
as near as possible to the
processor with an oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled into the oscilloscope probe.
4. For low BW bus connection between processor and PCH -> Vcc
IO
=0.85V.
5. For high BW bus connection between processor and PCH -> Vcc
IO
=0.95V.
6. OS occurs during power on only, not during normal operation
7. For Voltage less than 1V, TOB will be 50 mV.
Table 7-7. Vcc Sustain (Vcc
ST
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Units Notes
1,2
Vcc
ST
Processor Vcc Sustain
supply voltage
S with PCH Z370 — 1.0 — V 3
TOB
ST
Vcc
ST
Tol er an ce A ll AC + DC :± 5 % 3, 4
Icc
MAX_ST
Max Current for Vcc
ST
S-Processor Lines — — 80 mA
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured on package pins as near as possible to the processor with an
oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the
oscilloscope probe.
4. For Voltage less than 1V, TOB will be 50 mV.
Table 7-8. Processor PLL (Vcc
PLL
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Unit Notes
1,2
Vcc
PLL
PLL supply voltage (DC + AC
specification)
S with PCH Z370 — 1.0 — V 3
TOB
CCPLL
Vcc
PLL
Tolerance All AC+DC:± 5 % 3,4
Icc
MAX_VCCPLL
Max Current for Vcc
PLL
Rail S-Processor Lines — — 150 mA
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured on package pins as near as possible to the processor with an
oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the
oscilloscope probe.
4. For Voltage less than 1V, TOB will be 50 mV.
Table 7-6. Processor I/O (Vcc
IO
) Supply DC Voltage and Current Specifications (Sheet 2
of 2)
Symbol Parameter Segment Min Typ Max Unit
Note
1,2