Specification Sheet
Electrical Specifications
112 Datasheet, Volume 1 of 2
7.2.1.3 V
DDQ
DC Specifications
DC_LL
Vcc
GT
Loadline
slope
S-Quad Core GT2
S-Hexa Core GT2
—
—
—
—3.1
3.1
m
7, 9,
10
AC_LL
(S-
Processors)
AC Loadline
S-Processor Line
— —
Same as Max DC_LL (up to
400 KHz)
m
7, 9,
10
T_OVS_MAX
Max Overshoot
time
—
— — 10 s
V_OVS_MAX Max Overshoot — — — 70 mV
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and
cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the
same frequency may have different settings within the VID range. This differs from the VID employed by the processor
during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or
low-power states).
3. The voltage specification requirements are measured across Vcc
GT
_
SENSE
and Vss
GT
_
SENSE
as near as possible to the
processor with an oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled into the oscilloscope probe.
4. PSx refers to the voltage regulator power state as set by the SVID protocol.
5. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and
cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the
same frequency may have different settings within the VID range. This differs from the VID employed by the processor
during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or
low-power states).
6. N/A
7. LL measured at sense points.
8. Operating voltage range in steady state.
9. LL specification values should not be exceeded. If exceeded, power, performance and reliability penalty are expected.
10. Load Line (AC/DC) should be measured by the VRTT tool and programmed accordingly via the BIOS Load Line override setup
options. AC/DC Load Line BIOS programming directly affects operating voltages (AC) and power measurements (DC). A
superior board design with a shallower AC Load Line can improve on power, performance, and thermals compared to boards
designed for POR impedance.
Table 7-4. Memory Controller (V
DDQ
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Unit Note
1
V
DDQ (DDR4)
Processor I/O supply voltage for
DDR4
All
Typ-5% 1.20 Typ+5% V 3, 4, 5
TOB
VDDQ
VDDQ Tolerance All AC+DC:± 5 % 3, 4, 6
Icc
MAX_VDDQ
(DDR4)
Max Current for V
DDQ
Rail
(DDR4)
S
—— A 2
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. The current supplied to the DIMM modules is not included in this specification.
3. Includes AC and DC error, where the AC noise is bandwidth limited to under 100 MHz, measured on package pins.
4. No requirement on the breakdown of AC versus DC noise.
5. The voltage specification requirements are measured as near as possible to the processor with an oscilloscope set to 100-
MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire
on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
6. For Voltage less than 1V, TOB will be 50 mV.
Table 7-3. Processor Graphics (Vcc
GT
) Supply DC Voltage and Current Specifications
(Sheet 2 of 2)
Symbol Parameter Segment Min Typ Max
Unit Note
1