Specification Sheet

Datasheet, Volume 1 of 2 109
Electrical Specifications
7 Electrical Specifications
7.1 Processor Power Rails
7.1.1 Power and Ground Pins
All power pins should be connected to their respective processor power planes, while all
VSS pins should be connected to the system ground plane. Use of multiple power and
ground planes is recommended to reduce I*R drop.
7.1.2 V
CC
Voltage Identification (VID)
The processor uses three signals for the Serial Voltage IDentification (SVID) interface
to support automatic selection of voltages. The following table specifies the voltage
level corresponding to the 8-bit VID value transmitted over serial VID. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage
regulation circuit cannot supply the voltage that is requested, the voltage regulator
should disable itself. VID signals are CMOS push/pull drivers. See Tabl e 7- 1 4 for the DC
specifications for these signals. The VID codes will change due to temperature and/or
current load changes in order to minimize the power of the part. A voltage range is
provided in Section 7.2. The specifications are set so that one voltage regulator can
operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same processor IA core frequency may have different default VID settings. This
is shown in the VID range values in Section 7.2. The processor provides the ability to
operate while transitionally to an adjacent VID and its associated voltage. This will
represent a DC shift in the loadline.
Table 7-1. Processor Power Rails
Power Rail Description Control Availability
V
CC
Processor IA Cores Power Rail SVID All Processor Lines
Vcc
GT
Processor Graphics Power Rails SVID All Processor Lines
Vcc
SA
System Agent Power Rail SVID/Fixed (SKU dependent) All Processor Lines
Vcc
IO
IO Power Rail Fixed All Processor Lines
Vcc
ST
Sustain Power Rail Fixed All Processor Lines
Vcc
PLL
5
Processor PLLs power Rail Fixed All Processor Lines
Vcc
PLL_OC
3
Processor PLLs OC power Rail Fixed All Processor Lines
V
DDQ
Integrated Memory Controller Power Rail Fixed (Memory technology
dependent)
All Processor Lines
Notes:
1. N/A
2. N/A
3. Vcc
PLL_OC
power rail should be sourced from the VDDQ VR. The connection can be direct or through a load switch,
depending desired power optimization. In case of direct connection (Vcc
PLL_OC
is shorted to V
DDQ
, no load switch), platform
should ensure that Vcc
ST
is ON (high) while Vcc
PLL_OC
is ON (high).
4. Vcc
STG
power rail should be sourced from the VR as V
CCST
. The connection can be direct or through a load switch,
depending on desired power optimization.
5. Add 1 MHz LPF to reduce noise on power rail.