Specification Sheet

Signal Description
106 Datasheet, Volume 1 of 2
6.10 Power Sequencing Signals
THERMTRIP#
Thermal Trip: The processor protects itself from
catastrophic overheating by use of an internal thermal
sensor. This sensor is set well above the normal
operating temperature to ensure that there are no
false trips. The processor will stop all executions when
the junction temperature exceeds approximately
130 °C. This is signaled to the system by the
THERMTRIP# pin.
O OD SE All Processor Lines
Table 6-12. Power Sequencing Signals
Signal Name Description Dir. Buffer Type
Link
Type
Availability
PROCPWRGD
Processor Power Good: The processor
requires this input signal to be a clean
indication that the V
CC
and V
DDQ
power supplies
are stable and within specifications. This
requirement applies regardless of the S-state of
the processor. 'Clean' implies that the signal will
remain low (capable of sinking leakage
current), without glitches, from the time that
the power supplies are turned on until they
come within specification. The signal should
then transition monotonically to a high state.
I CMOS SE All Processor Lines
VCCST_PWRGD
VCCST Power Good: The processor requires
this input signal to be a clean indication that
the VCCST and VDDQ power supplies are stable
and within specifications. This signal should
have a valid level during both S0 and S3 power
states. 'Clean' implies that the signal will
remain low (capable of sinking leakage
current), without glitches, from the time that
the power supplies are turned on until they
come within specification. The signal should
then transition monotonically to a high state.
I CMOS SE All Processor Lines
PROC_DETECT#
/SKTOCC#
Processor Detect / Socket Occupied: Pulled
down directly (0 Ohms) on the processor
package to the ground. There is no connection
to the processor silicon for this signal. System
board designers may use this signal to
determine if the processor is present.
N/A N/A SE All Processor Lines
VIDSOUT
VIDSCK
VIDALERT#
VIDSOUT, VIDSCK, VIDALERT#: These
signals comprise a three-signal serial
synchronous interface used to transfer power
management information between the
processor and the voltage regulator controllers.
I/O
O
I
I:GTL/O:OD
OD
CMOS
SE All Processor Lines
PM_SYNC
Power Management Sync: A sideband signal
to communicate power management status
from the PCH to the processor. PCH report
EXTTS#/EVENT# status to the processor.
I CMOS SE S-Processor Line
PM_DOWN
Power Management Down: Sideband to
PCH. Indicates processor wake up event
EXTTS# on PCH. The processor combines the
pin status into the OLTM/CLTM.
O CMOS SE S-Processor Line
Table 6-11. Error and Thermal Protection Signals (Sheet 2 of 2)
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability