Specification Sheet

Datasheet, Volume 1 of 2 105
Signal Description
6.8 Testability Signals
6.9 Error and Thermal Protection Signals
Table 6-10. Testability Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
BPM#[3:0]
Breakpoint and Performance Monitor Signals:
Outputs from the processor that indicate the status
of breakpoints and programmable counters used for
monitoring processor performance.
I/O GTL SE All Processor Lines
PROC_PRDY#
Probe Mode Ready: PROC_PRDY# is a processor
output used by debug tools to determine processor
debug readiness.
O OD SE All Processor Lines
PROC_PREQ#
Probe Mode Request: PROC_PREQ# is used by
debug tools to request debug operation of the
processor.
I GTL SE All Processor Lines
PROC_TCK
Test Clock: This signal provides the clock input for
the processor Test Bus (also known as the Test
Access Port). This signal should be driven low or
allowed to float during power on Reset.
I GTL SE All Processor Lines
PROC_TDI
Test Data In: This signal transfers serial test data
into the processor. This signal provides the serial
input needed for JTAG specification support.
I GTL SE All Processor Lines
PROC_TDO
Test Data Out: This signal transfers serial test data
out of the processor. This signal provides the serial
output needed for JTAG specification support.
O OD SE All Processor Lines
PROC_TMS
Test Mode Select: A JTAG specification support
signal used by debug tools.
I GTL SE All Processor Lines
PROC_TRST#
Test Reset: Resets the Test Access Port (TAP) logic.
This signal should be driven low during power on
Reset.
I GTL SE All Processor Lines
Table 6-11. Error and Thermal Protection Signals (Sheet 1 of 2)
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
CATERR#
Catastrophic Error: This signal indicates that the
system has experienced a catastrophic error and
cannot continue to operate. The processor will set this
signal for non-recoverable machine check errors or
other unrecoverable internal errors. CATERR# is used
for signaling the following types of errors: Legacy
MCERRs, CATERR# is asserted for 16 BCLKs. Legacy
IERRs, CATERR# remains asserted until warm or cold
reset.
O OD SE All Processor Lines
PECI
Platform Environment Control Interface: A serial
sideband interface to the processor. It is used
primarily for thermal, power, and error management.
I/O
PECI,
Async
SE All Processor Lines
PROCHOT#
Processor Hot: PROCHOT# goes active when the
processor temperature monitoring sensor(s) detects
that the processor has reached its maximum safe
operating temperature. This indicates that the
processor Thermal Control Circuit (TCC) has been
activated, if enabled. This signal can also be driven to
the processor to activate the TCC.
I/O
GTL I
OD O
SE All Processor Lines