Specification Sheet

Electrical Specifications
52 Datasheet, Volume 1 of 2
5.5.2.3 System Reference Clock (BCLK{0/1/2}) DC Specifications
R
ON High impedance leakage to GND (V
leak
= V
OH
)
41 11 
C
Bus Bus capacitance per node — 10 pF 5
V
Noise Signal noise immunity above 300 MHz 0.100*
V
CCIO —
V
p-p
Output Edge Rate (50 ohm to V
SS
,
between
V
IL and V
IH
)
515V/ns
Notes:
1. The input voltage range specifies an overshoot/undershoot that applies only to the PECI data signal and not to the V
TT
reference itself.
2. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and consequently, be
able to drive its output within safe limits (-0.150 V to 0.275*V
CCIO
for the low level and 0.725*V
CCIO
to V
CCIO
+0.150 V for
the high level).
3. V
CCIO nominal levels will vary between processor families. All PECI devices will operate at the VCCIO level determined by the
processor installed in the system.
4. The leakage specification applies to powered devices on the PECI bus.
5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum
bit rate at which the interface can operate.
Symbol Parameter Signal Min Max Unit Figure Notes
1
V
BCLK_diff_ih Differential Input High
Voltage
Differential
0.150 N/A V
Figure 5-3 9
V
BCLK_diff_il Differential Input Low
Voltage
Differential
— -0.150 V
Figure 5-3 9
V
cross
(abs) Absolute Crossing Point Single Ended
0.250 0.550 V
Figure 5-4 and
Figure 5-5
2, 4, 7,
9
V
cross
(rel) Relative Crossing Point Single Ended 0.250 +
0.5*(VHavg -
0.700)
0.550 +
0.5*(VH
avg -
0.700)
V
Figure 5-4 3, 4, 5,
9
Δ
V
cross Range of Crossing Points Single Ended N/A 0.140 V Figure 5-6 6, 9
V
TH Threshold Voltage Single Ended Vcross - 0.1 Vcross + 0.1 V 9
I
IL Input Leakage Current N/A — 1.50 mA 8, 9
C
pad Pad Capacitance N/A 1.90 1.72 pF 9
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling
edge of BCLK{0/1}_DP.
3. V
Havg
is the statistical average of the VH measured by the oscilloscope.
4. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5. V
Havg
can be measured directly using “Vtop” on Agilent* and “High” on Tektronix oscilloscopes.
6. V
CROSS
is defined as the total variation of all crossing voltages as defined in Note 3.
7. The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP.
8. For Vin between 0 and Vih.
9. Specifications can be validated at the pin.
Symbol Definition and Conditions Min Max Units Figure Notes
1