Specification Sheet

Datasheet, Volume 1 of 2 51

Electrical Specifications
5.5.2.2 PECI DC Specifications
Reference Clock Signal
R
ON DDR4 Clock Buffer On Resistance 25.5 30 34.5 ohm 6
Command Signals
R
ON DDR4 Command Buffer On
Resistance
15.3 18 20.7 ohm
6, 11
R
ON DDR4 Reset Buffer On Resistance 76.5 90 103.5 ohm 6
V
OL_CMOS1.2V Output Low Voltage, Signals
DDR_RESET_C{01/23}_N
— — 0.2*V
CCD
V
1, 2
V
OH_CMOS1.2V Output High Voltage, Signals
DDR_RESET_C{01/23}_N
0.9*V
CCD
——V
1, 2
Control Signals
R
ON DDR4 Control Buffer On
Resistance
25.5 30 34.5 ohm
6
DDR4 Miscellaneous Signals
DRAM_PWR_OK_C{01/23}
V
IL Input Low Voltage — 0.3*VCCD — mV 2, 3
V
IH Input High Voltage — 0.7*VCCD — mV 2, 4, 5
ALERT_N
V
IL Input Low Voltage Vref-90 — Vref - 70 mV 3
V
IH Input High Voltage Vref+70 — Vref+90 mV 4
ODT On Die Termination 36 45 54 ohms
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The voltage rail V
CCD
which will be set to 1.2 V nominal depending on the voltage of all DIMMs connected to the processor.
3. V
IL
is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
4. V
IH
is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
5. V
IH
and V
OH
may experience excursions above V
CCD
. However, input signal drivers must comply with the signal quality
specifications.
6. This is the pull down driver resistance. Reset drive does not have a termination.
7. R
VTT_TERM
is the termination on the DIMM and not controlled by the processor. Please refer to the applicable DIMM
datasheet.
8. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
9. Input leakage current is specified for all DDR4 signals.
10. Vol = Ron * [VCCD/(Ron + Rtt_Eff)], where Rtt_Eff is the effective pull-up resistance of all DIMMs in the system, including
ODTs and series resistors on the DIMMs.
11. This Ron value is only for UDIMM, otherwise the Ron Value is 30 ohm.
Symbol Definition and Conditions Min Max Units Figure Notes
1
V
In Input Voltage Range -0.15
0.15 + V
CCIO V1
V
Hysteresis Hysteresis 0.1*
V
CCIO —V
V
N
Negative-edge threshold voltage 0.275*
V
CCIO 0.500*
V
CCIO V Figure 5-1 2
V
P
Positive-edge threshold voltage 0.550*
V
CCIO 0.725*
V
CCIO V Figure 5-1 2
I
Source Pullup Resistance (V
OH
= 0.75*
V
CCIO
)
-6.00 — mA
I
Leak+ High impedance state leakage to
V
CCIO
(V
leak
=
V
OL
)
±50 ±200 µA
3, 4
Symbol Parameter Min Nom Max Units Notes
1