Specification Sheet

Datasheet, Volume 1 of 2 5
Figures
1-1 Platform Block Diagram Example ...........................................................................8
1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 3 (DMI3) .................. 11
2-1 PCI Express* Layering Diagram........................................................................... 18
2-2 Packet Flow through the Layers........................................................................... 18
5-1 Input Device Hysteresis ..................................................................................... 36
5-2 VCCIN Static and Transient Tolerance Load Lines 1.0 mOHM ................................... 50
5-3 BCLK{0/1/2} Differential Clock Measurement Point for Ringback.............................. 53
5-4 BCLK{0/1/2} Differential Clock Crosspoint Specification ......................................... 53
5-5 BCLK{0/1/2} Single Ended Clock Measurement Points for Absolute 
Cross Point and Swing ....................................................................................... 53
5-6 BCLK{0/1/2} Single Ended Clock Measure Points for Delta Cross Point ..................... 54
Tables
1-1 Terminology ..................................................................................................... 13
1-2 Related Documents ........................................................................................... 15
4-1 Memory Channel DDR0, DDR1, DDR2, DDR3, DDR4, DDR5 ..................................... 28
4-2 Memory Channel Miscellaneous ........................................................................... 29
4-3 PCI Express Signals ........................................................................................... 29
4-4 PCI Express Miscellaneous Signals ....................................................................... 29
4-5 DMI3 Signals .................................................................................................... 29
4-6 PECI Signal ...................................................................................................... 30
4-7 System Reference Clock (BCLK{0/1/2}) Signals .................................................... 30
4-8 JTAG and TAP Signals ........................................................................................ 30
4-9 SVID Signals .................................................................................................... 31
4-10 Processor Asynchronous Sideband Signals .......................................................... 31
4-11 Miscellaneous Signals......................................................................................... 32
4-12 Power and Ground Signals.................................................................................. 34
5-1 Power and Ground Lands.................................................................................... 37
5-2 SVID Address Usage Bus 1 ................................................................................. 40
5-3 SVID Address Usage Bus 2 ................................................................................. 41
5-4 VR13.0 Reference Code Voltage Identification (VID) Table ...................................... 41
5-5 Signal Description Buffer Types ........................................................................... 42
5-6 Signal Groups ................................................................................................... 43
5-7 Signals with On-Die Weak PU/PD......................................................................... 45
5-8 Power-On Configuration Option Lands .................................................................. 45
5-9 Processor Absolute Minimum and Maximum Ratings ............................................... 46
5-10 Storage Condition Ratings .................................................................................. 47
5-11 Voltage Specification.......................................................................................... 47
5-12 Current (ICCIN_MAX and ICCIN_TDC) Specification ............................................... 48
5-13 VCCIN Static and Transient Tolerance for 1.0LL ..................................................... 49