Specification Sheet

Datasheet, Volume 1 of 2 45

Electrical Specifications
5.3.1 Power-On Configuration (POC) Options
Several configuration options can be configured by hardware. The processor samples
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, see the following table.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
Table 5-7. Signals with On-Die Weak PU/PD
Signal Name Pull Up/Pull Down Rail Value Units Notes
BIST_ENABLE Pull Up
V
CCIO 3K-8K 
BMCINIT Pull Down VSS 3K-8K 
DEBUG_EN_N Pull Up
V
CCIO 3K-8K 
DMIMODE_OVERRIDE Pull Up
V
CCIO 3K-8K 
EAR_N Pull Up
V
CCIO 3K-8K 
FRMAGENT Pull Down VSS 3K-8K 
LEGACY_SKT Pull Down VSS 3K-8K 
MSMI_N Pull Up
V
CCIO 3K-8K 
NMI Pull Down VSS 3K-8K 
PM_FAST_WAKE_N Pull Up
V
CCIO 3K-8K 
PROCDIS_N Pull Up
V
CCIO 3K-8K 
SAFE_MODE_BOOT Pull Down VSS 3K-8K 
SOCKET_ID[2:0] Pull Down VSS 3K-8K 
TCK Pull Down VSS 3K-8K 
TDI Pull Up
V
CCIO 3K-8K 
TMS Pull Up
V
CCIO 3K-8K 
TRST_N Pull Up
V
CCIO 3K-8K 
TXT_AGENT Pull Down VSS 3K-8K 
TXT_PLTEN Pull Up
V
CCIO 3K-8K 
Table 5-8. Power-On Configuration Option Lands (Sheet 1 of 2)
Configuration Option Land Name Notes
Output tri state PROCDIS_N 1
Execute BIST (Built-In Self Test) BIST_ENABLE 2
Enable Service Processor Boot Mode BMCINIT 3
Power-up Sequence Halt EAR_N 3
Enable Intel
®
Trusted Execution Technology (Intel
®
TXT)
Platform
TXT_PLTEN 3
Enable Bootable Firmware Agent FRMAGENT 3