Specification Sheet

Electrical Specifications
44 Datasheet, Volume 1 of 2
System Reference Clock (BCLK{0/1/2})
Differential CMOS 1.05 V Input BCLK{0/1/2}_D[N/P]
JTAG & TAP Signals
Single ended CMOS Input
TCK,TDI,TMS,TRST_N,PREQ_N
Open Drain Output /CMOS
Input
BPM_N[7:0]
Open Drain Output
TDO, PRDY_N
Serial VID Interface (SVID) Signals
Single ended CMOS Input
SVIDALERT_N[1:0]
Open Drain Output / CMOS
Input
SVIDDATA [1:0]
Open Drain Output
SVIDCLK [1:0]
Processor Asynchronous Sideband Signals
Single ended CMOS Input
BIST_ENABLE, BMCINIT, DEBUG_EN_N
FRMAGENT, PWRGOOD, PMSYNC
RESET_N, SAFE_MODE_BOOT,
SOCKET_ID[1:0], TXT_AGENT
TXT_PLTEN
CMOS Output FIVR_FAULT
Open Drain Output / CMOS
Input
CATERR_N, MEM_HOT_C01_N,
MEM_HOT_C23_N, MSMI_N,
PM_FAST_WAKE_N, PROCHOT_N
Open Drain Output ERROR_N[2:0], THERMTRIP_N
Miscellaneous Signals
CMOS Input EAR_N,LEGACY_SKT,NMI,PMSYNCPMSY
NC_CLK,PROCDIS_N,
PWR_DEBUG_N,SOCKET_ID2
Open Drain Output / CMOS
Input
TSC_SYNC
Not connected to Silicon SKTOCC_N,PKGID[2:0], PROC_ID[1:0]
Power/Other Signals
Power / Ground
V
CCIN
, V
CCD_012
, V
CCD_345
, V
CCIO
,
V
CC33
, V
CC33
, V
SS
Sense Points VCCIN_SENSE, VCCIO_SENSE,
VCCSA_SENSE,
VSS_VCCIN_SENSE,
VSS_VCCIO_SENSE,
VSS_VCCSA_SENSE,
VCCIN_PMAX, VSENSEPMAX
Notes:
1. Refer to Chapter 4, “Signal Descriptions” for signal description details.
2. DDR{0/1/2/3/4/5} refers to DDR4 Channel 0, DDR4 Channel 1, DDR4 Channel 2, DDR4 Channel 3, DDR4
Channel 4 and DDR4 Channel 5.
Table 5-6. Signal Groups (Sheet 2 of 2)
Differential/Single Ended Buffer Type Signal