Specification Sheet

Datasheet, Volume 1 of 2 43
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Electrical Specifications
Table 5-6. Signal Groups (Sheet 1 of 2)
Differential/Single Ended Buffer Type Signal
DDR4 Reference Clocks
Differential SSTL Output DDR{0/1/2/3/4/5}_CLK_D[N/P] [3:0]
DDR4 Command Signals
Single-ended SSTL Output DDR{0/1/2/3/4/5}_ACT_N DDR{0/1/2/
3/4/5}_BA[1:0] DDR{0/1/2/3/4/
5}_BG[1:0] DDR{0/1/2/3/4/
5}_MA[17:0] DDR{0/1/2/3/4/5}_PAR
DDR4 Control Signals
Single-ended SSTL Output DDR{0/1/2/3/4/5}_CS_N[7:0] DDR{0/
1/2/3/4/5}_CID[2] DDR{0/1/2/3/4/
5}_ODT[3:0] DDR{0/1/2/3/4/
5}_CKE[3:0]
DDR4 Data Signals
Differential SSTL Input/Output DDR{0/1/2/3/4/5}_DQS_D[N/P] [17:0]
Single-ended SSTL Input/Output DDR{0/1/2/3/4/5}_DQ[63:0] DDR{0/
1/2/3/4/5}_ECC[7:0]
DDR4 Miscellaneous Signals
Single-ended SSTL Input DDR{0/1/2/3/4/5}_ALERT_N
CMOS Input
Note: Input voltage from
platform cannot exceed 1.2 V
max.
DDR{012,345}_DRAM_PWR_OK
CMOS 1.2 V Output DDR{012,345}_RESET_N
Open Drain Output / CMOS
Input
DDR[012,345]_SPDSCL
DDR[012,345]_SPDSDA
DC Output DDR{5:0}_CAVREF
DDR Compensation resistance
control
DDR{012,345}_RCOMP[2:0]
PCI Express* Port 1, 2, & 3 Signals
Differential PCI Express* Input PE{3:1}_RX_DN/DP[15:0]
Differential PCI Express* Output PE{3:1}_TX_DN/DP[15:0]
PCI Express* Miscellaneous Signals
Single-ended
Open Drain Output PE_HP_SCL
Open Drain Output /CMOS
Input
PE_HP_SDA
DMI3/PCI Express* Signals
Differential DMI3 Input DMI3_RX_D[N/P][3:0]
DMI3 Output DMI3_TX_D[N/P][3:0]
Single-ended DMI Miscellaneous DMIMODE_OVERRIDE
Platform Environmental Control Interface (PECI)
Single-ended PECI Input/Output PECI