Specification Sheet

ManualsBrandsINTEL ManualsPC ComponentsWOF processor Core i7 i7-7800X 6 x 3.5 GHz H

Electrical Specifications

42 Datasheet, Volume 1 of 2

5.2.9 Reserved or Unused Signals

All Reserved (RSVD) signals must not be connected. Connection of these signals to

CCIN

, V

CCD

, V

, or to any other signal (including each other) can result in component

malfunction or incompatibility with future processors.

For reliable operation, always connect unused inputs or bi-directional signals to an

appropriate signal level. Unused active high inputs should be connected through a

resistor to ground (V

). Unused outputs maybe left unconnected; however, this may

interfere with some Test Access Port (TAP) functions, complicate debug probing, and

prevent boundary scan testing. A resistor must be used when tying bi-directional

signals to power or ground. When tying any signal to power or ground, a resistor will

also allow for system testability.

5.3 Signal Group Summary

Signals are grouped by buffer type and similar characteristics as listed in the following

table. The buffer type indicates which signaling technology and specifications apply to

the signals.

1E 0.79 3E 1.11 5E 1.43 7E 1.75 9E 2.07 BE 2.39 DE 2.71 FE 3.03

1F 0.80 3F 1.12 5F 1.44 7F 1.76 9F 2.08 BF 2.40 DF 2.72 FF 3.04

Notes:

1. 00h = Off State

2. VID Range HEX 65-97 are not used by the

processor

3. VCCD can use Protocol ID of 10 mV or 5 mV.

4. VCCD can use VID Ta bl e 5 - 4 .

Table 5-4. VR13.0 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2)

HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN

Table 5-5. Signal Description Buffer Types

Signal Description

Analog Analog reference or output. May be used as a threshold voltage or for buffer

compensation

Asynchronous Signal has no timing relationship with any system reference clock.

CMOS CMOS Output buffers: 1.05 V tolerant / CMOS Input buffers

DDR4 CMOS Output buffers 1.2 V tolerant

DMI3 Direct Media Interface Gen 3 signals. These signals are compatible with PCI Express* 3.0

Signaling Environment AC Specifications.

Open Drain Open Drain buffers: 1.05 V tolerant

PCI Express* PCI Express interface signals. These signals are compatible with PCI Express 3.0 Signaling

Environment AC Specifications and are AC coupled. The buffers are not 3.3-V tolerant.

Refer to the PCIe specification.

Reference Voltage reference signal.

SSTL Source Series Terminated Logic (JEDEC SSTL_15)

Note: Qualifier for a buffer type.