Specification Sheet

Electrical Specifications
40 Datasheet, Volume 1 of 2
The SetVID_Fast command is preemptive. The VR interrupts its current processes and
moves to the new VID. The SetVID_Fast command operates on 1 VR address at a time.
This command is used in the processor for package C6 fast exit.
5.2.8.7 SetVID Slow
The SetVID_Slow command contains the target VID in the payload byte. The range of
voltage is defined in the VID table. The VR should ramp to the new VID setting with a
“slow” slew rate as defined in the slow slew rate data register. The SetVID_Slow is
nominally 4x slower than the SetVID_Fast slew rate.
The SetVID_Slow command is preemptive, the VR interrupts its current processes and
moves to the new VID. This is the instruction used for normal P-state voltage change.
This command is used in the processor for the Intel Enhanced SpeedStep Technology
transitions.
5.2.8.8 SetVID Decay
The SetVID_Decay command is the slowest of the DVID transitions. It is only used for
VID down transitions. The VR does not control the slew rate, the output voltage
declines with the output load current only.
The SetVID_Decay command is preemptive, the VR interrupts its current processes and
moves to the new VID. This command is used in the processor for package C6 entry,
allowing capacitor discharge by the leakage, thus saving energy.This command is only
used in VID down direction in the processor package C6 entry.
5.2.8.9 SVID Voltage Rail Addressing
The processor addresses 4 different voltage rail control segments within VR13.0 (V
CCIN
,
V
CCD
, V
CCSA
, and V
CCIO
). The SVID data packet contains a 4-bit addressing code.
Table 5-2. SVID Address Usage Bus 1
PWM Address (HEX) Protocol ID Processor
00 04H(10 mV VID)
V
CCIN
01 07H(5 mV VID)
V
CCSA
02 07H(5 mV VID)
V
CCIO
03 N/A Reserved for optional rail
04 Reserved for optional rail
05 Reserved for optional rail
Notes:
1. Check with VR vendors for determining the physical address assignment method for their controllers.
2. VR addressing is assigned on a per voltage rail basis.
3. Dual VR controllers will have two addresses with the lowest order address, always being the higher
phase count.
4. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not
used.