Specification Sheet

Electrical Specifications
38 Datasheet, Volume 1 of 2
5.2.8.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full power states. This may
cause voltages on power planes to sag below their minimum values if bulk decoupling is
not adequate. Large electrolytic bulk capacitors (CBULK), help maintain the output
voltage during current transients, for example coming out of an idle condition. Care
must be taken in the baseboard design to ensure that the voltages provided to the
processor remain within the specifications listed in Table 5-11, “Voltage Specification”.
Failure to do so can result in timing violations or reduced lifetime of the processor.
5.2.8.3 Voltage Identification (VID)
The Voltage Identification (VID) specification for the V
CCIN
, VSA, voltage is defined by
the VR13.0 PWM. The reference voltage or the VID setting is set using the SVID
communication bus between the processor and the voltage regulator controller chip.
The VID settings are the nominal voltages to be delivered to the processor's lands. The
VR 13.0 Reference Code Voltage Identification Table specifies the reference voltage
level corresponding to the VID value transmitted over serial VID. The VID codes will
change due to temperature and/or current load changes in order to minimize the power
and to maximize the performance of the part. The specifications are set so that a
voltage regulator can operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
processor units with the same core frequency may have different default VID settings.
The processor uses voltage identification signals to support automatic selection of a
power supply voltage. If the processor socket is empty (SKTOCC_N high), or a “not
supported” response is received from the SVID bus, then the voltage regulation circuit
cannot supply the voltage that is requested, the voltage regulator must disable itself or
not power on. Vout MAX register (30h) is programmed by the processor to set the
maximum supported VID code and if the programmed VID code is higher than the VID
supported by the VR, then VR will respond with a “not supported” acknowledgment.
5.2.8.4 SVID Commands
The processor provides the ability to operate while transitioning to a new VID setting
and its associated processor voltage rail. This is represented by a DC shift. It should be
noted that a low-to-high or high-to-low voltage state change may result in as many
VID transitions as necessary to reach the target voltage. Transitions above the
maximum specified VID are not supported. The processor supports the following VR
commands:
• SetVID_Fast (25 mV/µs for VCCIN, 10mV for VSA,VCCIO)
• SetVID_Slow is 1/4 of SetVID_Fast
• SetVID_Decay (downward voltage only and it's a function of the output
capacitance's time constant) commands. The VR 13.0 Reference Code Voltage
Identification Table includes SVID step sizes and DC shift ranges. Minimum and
maximum voltages must be maintained as shown in
Tab l e 5-11. This is a CSR
configuration option.
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID.