Specification Sheet

Datasheet, Volume 1 of 2 35

Electrical Specifications
5 Electrical Specifications
This chapter describes processor signaling and DC specifications. References to various
interfaces (memory, PCIe* PECI, and so forth) are also described.
5.1 Integrated Voltage Regulation
The platform voltage regulator is integrated into the processor. Due to this integration,
the processor has one main voltage rail (V
CCIN
) and a voltage rail for the memory
interface (V
CCD012,
V
CCD345
- one for each memory channel pair). The V
CCIN
voltage rail
will supply the integrated voltage regulators which in turn will regulate to the
appropriate voltages for the cores, cache, and system agents. This integration allows
the processor to better control on-die voltages to optimize for both performance and
power savings. The processor V
CCIN
rail will remain a VID -based voltage with a loadline
similar to the core voltage rail (called V
CC
) in previous processors. In addition to the
above, the processor has voltage rails VCCIO for IO, VCCSA for the System Agent, and
VCC33 for PIROM.
5.2 Processor Signaling
The processor includes 2066 lands, which utilize various signaling technologies. Signals
are grouped by electrical characteristics and buffer type into various signal groups.
These include DDR4 (Reference Clock, Command, Control, and Data), PCI Express*,
DMI3, Platform Environmental Control Interface (PECI), System Reference Clock,
SMBus, JTAG and Test Access Port (TAP), SVID Interface, Processor Asynchronous
Sideband, Miscellaneous, and Power/ Other signals. See Table 5-6 for details.
Intel strongly recommends performing analog simulations of all interfaces.
5.2.1 System Memory Interface Signal Groups
The system memory interface utilizes DDR4 technology, which consists of numerous
signal groups. These include: Reference Clocks, Command Signals, Control Signals,
and Data Signals. Each group consists of numerous signals, which may utilize various
signaling technologies. See Table 5-6 for further details.
Throughout this chapter the system memory interface may be referred to as DDR4.
5.2.2 PCI Express* Signals
The PCI Express Signal Group consists of PCI Express* ports 1, 2, and 3, and PCI
Express miscellaneous signals. See Table 5-6 for further details.
5.2.3 DMI3/PCI Express* Signals
The Direct Media Interface Gen 3(DMI3) sends and receives packets and/or commands
to the PCH. The DMI3 is an extension of the standard PCI Express Specification. The
DMI3/PCI Express Signals consist of DMI3 receive and transmit input/output signals
and a control signal to select DMI3 or PCIe* 3.0 operation for port 0. See Table 5-6 for
further details.