Specification Sheet

Datasheet, Volume 1 of 2 31
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Signal Descriptions
4.7 Serial VID Interface (SVID) Signals
4.8 Processor Asynchronous Sideband and
Miscellaneous Signals
Table 4-9. SVID Signals
Signal Name Description
SVIDALERT_N [1:0] Serial VID alert.
SVIDCLK [1:0] Serial VID clock.
SVIDDATA [1:0] Serial VID data out.
Table 4-10. Processor Asynchronous Sideband Signals (Sheet 1 of 2)
Signal Name Description
CATERR_N
Indicates that the system has experienced a fatal or catastrophic error and
cannot continue to operate. The processor will assert CATERR_N for
unrecoverable machine check errors and other internal unrecoverable
errors. It is expected that every processor in the system will wire-OR
CATERR_N for all processors. Since this is an I/O land, external agents are
allowed to assert this land which will cause the processor to take a machine
check exception. The CATERR_N signal can be sampled any time after 1.5
ms after the assertion of PWRGOOD. On Skylake, CATERR_N is used for
signaling the following types of errors:
• Legacy MCERR's, CATERR_N is asserted for 16 BCLKs.
ERROR_N[2:0]
Error status signals for integrated I/O (IIO) unit:
0 = Hardware correctable error (no operating system or firmware action
necessary)
1 = Non-fatal error (operating system or firmware action required to contain
and recover)
2 = Fatal error (system reset likely required to recover)
MEM_HOT_C{012/345}_N
Memory throttle control. Signals external BMC-less controller that DIMM is
exceeding temperature limit and needs to increase to maximum fan speed.
MEM_HOT_C012_N and MEM_HOT_C345_N signals have two modes of
operation - input and output mode.
Input mode is externally asserted and is used to detect external events such
as VR_HOT# from the memory voltage regulator and causes the processor
to throttle the appropriate memory channels.
Output mode is asserted by the processor known as level mode. In level
mode, the output indicates that a particular branch of memory subsystem is
hot.
MEM_HOT_C012_N is used for memory channels 0,1 & 2 while
MEM_HOT_C345_N is used for memory channels 3, 4 & 5.
MSMI_N
Machine Check Exception (MCE) is signaled using this pin when eMCA2 is
enabled. The MSMI_N signal can be sampled any time after 1.5 ms after the
assertion of PWRGOOD
PMSYNC
Power Management Sync. A sideband signal to communicate power
management status from the Platform Controller Hub (PCH) to the
processor.
PMSYNC_CLK 24 MHz SE Clock used for PCH PMSYNC.
PROCHOT_N
PROCHOT_N will go active when the processor temperature monitoring
sensor detects that the processor has reached its maximum safe operating
temperature. This indicates that the processor Thermal Control Circuit has
been activated, if enabled. This signal can also be driven to the processor to
activate the Thermal Control Circuit. This signal is sampled after PWRGOOD
assertion.