Specification Sheet

Signal Descriptions
30 Datasheet, Volume 1 of 2
4.4 PECI Signal
4.5 System Reference Clock Signals
4.6 JTAG and TAP Signals
Table 4-6. PECI Signal
Signal Name Description
PECI
PECI (Platform Environment Control Interface) is the serial sideband
interface to the processor and is used primarily for thermal, power and error
management.
Table 4-7. System Reference Clock (BCLK{0/1/2}) Signals
Signal Name Description
BCLK{0,1,2}_DN/DP
Reference Clock Differential input.
These pins provide the required reference inputs to various PLLs inside the
processor, such as PCIe. BCLK0, BCLK1 and BCLK2 run at 100 MHz from the
same clock source.
Table 4-8. JTAG and TAP Signals
Signal Name Description
BPM_N[7:0]
Breakpoint and Performance Monitor Signals: I/O signals from the processor
that indicate the status of breakpoints and programmable counters used for
monitoring processor performance. These are 100 MHz signals.
PRDY_N
Probe Mode Ready is a processor output used by debug tools to determine
processor debug readiness.
PREQ_N
Probe Mode Request is used by debug tools to request debug operation of
the processor.
TCK
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI
TDI (Test Data In) transfers serial test data into the processor. TDI provides
the serial input needed for JTAG specification support.
TDO
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TMS
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRST_N
TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must
be driven low during power on Reset.