Specification Sheet

Signal Descriptions
28 Datasheet, Volume 1 of 2
4 Signal Descriptions
This chapter describes the signals. They are arranged in functional groups according to
their associated interface or category.
4.1 System Memory Interface
Table 4-1. Memory Channel DDR0, DDR1, DDR2, DDR3, DDR4, DDR5
Signal Name Description
DDR{5:0}_ACT_N
Activate. When asserted, indicates MA[16:14] are command signals
(RAS_N, CAS_N, WE_N).
DDR{5:0}_ALERT_N Parity Error detected by the DIMM (one for each channel).
DDR{5:0}_BA[1:0]
Bank Address. Defines which bank is the destination for the current
Activate, Read, Write, or Precharge command.
DDR{5:0}_BG[1:0]
Bank Group: Defines which bank group is the destination for the current
Active, Read, Write or Precharge command. BG0 also determines which
mode register is to be accessed during a MRS cycle.
DDR{5:0}_CID[2] 3DS DRAM Chip ID signal
DDR{5:0}_CKE[3:0] Clock Enable.
DDR{5:0}_CLK_DN[3:0]
DDR{5:0}_CLK_DP[3:0]
Differential clocks to the DIMM. All command and control signals are valid on
the rising edge of clock.
DDR{5:0}_CS_N[7:0]
Chip Select. Each signal selects one rank as the target of the command and
address.
CS_N[7:6] are multiplexed with CID[4:3], respectively. CS_N[3:2] are
multiplexed with CID[1:0], respectively.
DDR{5:0}_DQ[63:0] Data Bus. DDR4 Data bits.
DDR{5:0}_DQS_DP[17:0]
DDR{5:0}_DQS_DN[17:0]
Data strobes. Differential pair, Data Strobe. Differential strobes latch data
for each DRAM. Different numbers of strobes are used depending on
whether the connected DRAMs are x4,x8. Driven with edges in center of
data, receive edges are aligned with data edges.
DDR{5:0}_MA[17:0]
Memory Address. Selects the Row address for Reads and writes, and the
column address for activates. Also used to set values for DRAM configuration
registers.
MA[16], MA[15], and MA[14] are multi-function and multiplexed with
RAS_N, CAS_N, and WE_N, respectively.
Note: MA[17] is not used on X-Series Processor It is reserved for future
processor implementations. The pin still requires to be routed appropriately
on the board to support future drop-in compatibility.
DDR{5:0}_PAR Even parity across Address and Command.
DDR{5:0}_ODT[3:0]
On Die Termination. Enables DRAM on die termination during Data Write or
Data Read transactions.
Note: Channels DDR2 and DDR5 are reserved on the HEDT Intel X-Series processor.