Specification Sheet
Datasheet, Volume 1 of 2 15
Introduction
1.8 Related Documents
Refer to the following documents for additional information.
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to "free air"
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
STR Suspend-to-RAM
SVID Serial Voltage Identification
TAC Thermal Averaging Constant
TCC Thermal Control Circuit
TDP Thermal Design Power
TLP Transaction Layer Packet
TSOD Temperature Sensor On DIMM
UDIMM Unbuffered Dual In-line Memory Module
Uncore
The portion of the processor comprising the shared LLC cache, IMC, HA, PCU,
Ubox, and IIO link interface.
Unit Interval
Signaling convention that is binary and unidirectional. In this binary signaling,
one bit is sent for every edge of the forwarded clock, whether it be a rising edge
or a falling edge. If a number of edges are collected at instances t
1
, t
2
, t
n
,....,
t
k
then the UI at instance "n" is defined as: UI
n
= t
n
- t
n-1
V
CCD
DDR power rail
V
CCIN
Primary voltage input to the voltage regulators integrated into the processor.
V
CCIO_IN
IO voltage supply input
VSS Processor ground
x1 Refers to a Link or Port with one Physical Lane
x16 Refers to a Link or Port with sixteen Physical Lanes
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
Table 1-1. Terminology (Sheet 3 of 3)
Term Description
Table 1-2. Related Documents (Sheet 1 of 2)
Document
Document Number/
Location
Intel
®
Core™ X-Series Processor Family Datasheet, Volume 2 of 2 335900
Intel
®
Core™ X-Series Processor Family Specification Update 335901
Advanced Configuration and Power Interface Specification 4.0 http://www.acpi.info/
PCI Local Bus Specification 3.0 http://www.pcisig.com/
PCI Express Base Specification, Revision 3.0
http://www.pcisig.com/ PCI Express Base Specification, Revision 2.1
PCI Express Base Specification, Revision 1.1