Specification Sheet

Datasheet, Volume 1 of 2 11

Introduction
1.3.3 Direct Media Interface
• Chip-to-chip interface to the PCH
• The DMI3 port supports x4 link width and only operates in a x4 mode when in DMI3
• Operates at PCI Express* 1.0, 2.0, 3.0 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of
Interrupt” broadcast message when initiated by the processor.
• System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI virtual channels VC0, VC1, VCm, and VCp
1.3.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH).
• Supports operation at up to 2 Mbps data transfers
• Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 3 (DMI3)
Transaction
Link
Physical
Port1
(PE1)
PCIe
0..3 4..7 8..11 12..15
x4 x4 x4 x4
Port1a Port1b Port1c Port1d
x8 x8
Port1a
Port1c
x16
Port1a
Transaction
Link
Physical
Port2
(PE2)
PCIe
0..3 4..7 8..11 12..15
x4 x4 x4 x4
Port2a Port2b Port2c Port2d
x8 x8
Port2a
Port2c
x16
Port2a
Transaction
Link
Physical
Port3
(PE3)
PCIe
0..3 4..7 12..15
x4 x4 x4
Port3a Port3b Port3d
x8
Port3d
x12
Port3b
x4
Port3b
0..3
x4
DMI
Link
Physical
Transaction
Port0
DMI/PCIe