User Manual

Electrical Specifications
50 Datasheet
5.4 Power-On Configuration (POC) Options
Several configuration options can be configured by hardware. The processor samples
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, refer to the following table.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed, except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
Table 5-6. Signals with On-Die Weak Pull-Up/Pull-Down Resistors
Signal Name Pull Up/Pull Down Rail Value Units Notes
BIST_ENABLE Pull Up VCCIO_IN 5K–15K 
BMCINIT Pull Down VSS 5K–15K 
DEBUG_EN_N Pull Up VCCIO_IN 5K–15K 
EAR_N Pull Up VCCIO_IN 5K–15K 
FRMAGENT Pull Down VSS 5K–15K 
PM_FAST_WAKE_N Pull Up VCCIO_IN 5K–15K 
PREQ_N Pull Up VCCIO_IN 5K–15K 
SAFE_MODE_BOOT Pull Down VSS 5K–15K 
SOCKET_ID[1:0] Pull Down VSS 5K–15K 
TCK Pull Down VSS 5K–15K 
TDI Pull Up VCCIO_IN 5K–15K 
TMS Pull Up VCCIO_IN 5K–15K 
TRST_N Pull Up VCCIO_IN 5K–15K 
TXT_AGENT Pull Down VSS 5K–15K 
TXT_PLTEN Pull Up VCCIO_IN 5K–15K 
Table 5-7. Power-On Configuration Option Lands
Configuration Option Land Name Notes
Output tri state PROCHOT_N
Execute BIST (Built-In Self Test) BIST_ENABLE 1
Enable Service Processor Boot Mode BMCINIT 2
Power-up Sequence Halt EAR_N 2
Enable Intel
®
Trusted Execution Technology (Intel
®
TXT)
Platform
TXT_PLTEN
2
Enable Bootable Firmware Agent FRMAGENT 2
Enable Intel Trusted Execution Technology (Intel TXT) Agent TXT_AGENT 2
Enable Safe Mode Boot SAFE_MODE_BOOT 2
Configure Socket ID SOCKET_ID[1:0] 2
Enables debug from cold boot DEBUG_EN_N 2
Note:
1. BIST_ENABLE is sampled at RESET_N de-assertion
2. This signal is sampled after PWRGOOD assertion.