User Manual

Datasheet 49

Electrical Specifications
JTAG & TAP Signals
Single ended
CMOS 1.05V Input
TCK
TDI
TMS
TRST_N
CMOS 1.05V Input/Output PREQ_N
CMOS1.05V Output PRDY_N
Open Drain CMOS Input/Output BPM_N[7:0]
Open Drain CMOS Output TDO
Serial VID Interface (SVID) Signals
Single ended
CMOS 1.05V Input SVIDALERT_N
Open Drain CMOS Input/Output SVIDDATA
Open Drain CMOS Output SVIDCLK
Processor Asynchronous Sideband Signals
Single ended
CMOS 1.05V Input
BIST_ENABLE
BMCINIT
DEBUG_EN_N
FRMAGENT
PWRGOOD
PMSYNC
RESET_N
SAFE_MODE_BOOT
SOCKET_ID[1:0]
TXT_AGENT
TXT_PLTEN
CMOS 1.05V Output FIVR_FAULT
Open Drain CMOS Input/Output
CATERR_N
MEM_HOT_C01_N
MEM_HOT_C23_N
MSMI_N
PM_FAST_WAKE_N
PROCHOT_N
Open Drain CMOS Output
ERROR_N[2:0]
THERMTRIP_N
Miscellaneous Signals
CMOS 1.05V Input EAR_N
Output SKTOCC_N
Power/Other Signals
Power / Ground
V
CCIN
, V
CCD_01
, V
CCD_23
, V
CCIO_IN
,
V
CCPECI
, V
SS
Sense Points
VCCIN_SENSE
VSS_VCCIN_SENSE
Notes:
1. Refer to Chapter 4, “Signal Descriptions” for signal description details.
2. DDR{0/1/2/3} refers to DDR4 Channel 0, DDR4 Channel 1, DDR4 Channel 2, and DDR4 Channel 3.
Table 5-5. Signal Groups (Sheet 3 of 3)
Differential/Single Ended Buffer Type Signal