User Manual

Electrical Specifications
42 Datasheet
5.2.8.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full power states. This may
cause voltages on power planes to sag below their minimum values if bulk decoupling is
not adequate. Large electrolytic bulk capacitors (CBULK) help maintain the output
voltage during current transients; for example, coming out of an idle condition. Care
must be taken in the baseboard design to ensure that the voltages provided to the
processor remain within the specifications listed in Table 5-10, “Voltage Specification”
on page 53. Failure to do so can result in timing violations or reduced lifetime of the
processor.
5.2.8.3 Voltage Identification (VID)
The reference voltage or the VID setting is set using the SVID communication bus
between the processor and the voltage regulator controller chip. The VID settings are
the nominal voltages to be delivered to the processor's V
CCIN
lands. Table 5-3, “VR12.5
Reference Code Voltage Identification (VID) Table” on page 45 specifies the reference
voltage level corresponding to the VID value transmitted over serial VID. The VID codes
will change due to temperature and/or current load changes in order to minimize the
power and to maximize the performance of the part. The specifications are set so that a
voltage regulator can operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
processor units with the same core frequency may have different default VID settings.
The processor uses voltage identification signals to support automatic selection of
V
CCIN
power supply voltage. If the processor socket is empty (SKTOCC_N high), or a
"not supported" response is received from the SVID bus, then the voltage regulation
circuit cannot supply the voltage that is requested. The voltage regulator must disable
itself or not power on. Vout MAX register (30h) is programmed by the processor to set
the maximum supported VID code and if the programmed VID code is higher than the
VID supported by the VR, then VR will respond with a "not supported"
acknowledgment.
5.2.8.4 SVID Commands
The processor provides the ability to operate while transitioning to a new VID setting
and its associated processor voltage rail (V
CCIN
). This is represented by a DC shift. It
should be noted that a low-to-high or high-to-low voltage state change may result in as
many VID transitions as necessary to reach the target voltage. Transitions above the
maximum specified VID are not supported. The processor supports the following VR
commands:
• SetVID_Fast (20 mV/µs)
• SetVID_Slow (5 mV/µs)
V
CCIO_IN
1 IO voltage supply input
V
CCPECI
1 Power supply for PECI.
V
SS
631 Ground
Table 5-1. Power and Ground Lands (Sheet 2 of 2)
Power and
Ground Lands
Number of
Lands
Comments