User Manual

4 Datasheet
4.3 Direct Media Interface 2 (DMI2) Signals................................................................33
4.4 Intel
®
QuickPath Interconnect (Intel
®
QPI) Signals ................................................34
4.5 Platform Environment Control Interface (PECI) Signal.............................................34
4.6 System Reference Clock Signals ..........................................................................34
4.7 JTAG and TAP Signals.........................................................................................34
4.8 Serial VID Interface (SVID) Signals ......................................................................35
4.9 Processor Asynchronous Sideband and Miscellaneous Signals...................................35
4.10 Processor Power and Ground Supplies ..................................................................38
5 Electrical Specifications ...........................................................................................39
5.1 Integrated Voltage Regulation .............................................................................39
5.2 Processor Signaling............................................................................................39
5.2.1 System Memory Interface Signal Groups....................................................39
5.2.2 PCI Express* Signals...............................................................................39
5.2.3 Direct Media Interface 2 (DMI2) / PCI Express* Signals ...............................39
5.2.4 Platform Environmental Control Interface (PECI).........................................40
5.2.4.1 Input Device Hysteresis .............................................................40
5.2.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) .........................40
5.2.6 JTAG and Test Access Port (TAP) Signals....................................................41
5.2.7 Processor Sideband Signals......................................................................41
5.2.8 Power, Ground and Sense Signals .............................................................41
5.2.8.1 Power and Ground Lands............................................................41
5.2.8.2 Decoupling Guidelines................................................................42
5.2.8.3 Voltage Identification (VID) ........................................................42
5.2.8.4 SVID Commands.......................................................................42
5.2.8.5 SetVID Fast Command...............................................................43
5.2.8.6 SetVID Slow .............................................................................43
5.2.8.7 SetVID Decay ...........................................................................43
5.2.8.8 SVID Power State Functions: SetPS .............................................43
5.2.8.9 SVID Voltage Rail Addressing......................................................44
5.2.8.10 Reserved or Unused Signals........................................................46
5.2.9 Reserved or Unused Signals .....................................................................46
5.3 Signal Group Summary.......................................................................................46
5.4 Power-On Configuration (POC) Options .................................................................50
5.5 Absolute Maximum and Minimum Ratings..............................................................51
5.5.1 Storage Conditions Specifications..............................................................51
5.6 DC Specifications...............................................................................................52
5.6.1 Die Voltage Validation .............................................................................55
5.6.1.1 V
CCIN
Overshoot Specifications....................................................55
5.6.2 Signal DC Specifications ..........................................................................56
5.6.2.1 DDR4 Signal DC Specifications ....................................................56
5.6.2.2 PECI DC Specifications ...............................................................58
5.6.2.3 System Reference Clock (BCLK{0/1}) DC Specifications .................58
5.6.2.4 SMBus DC Specifications ............................................................60
5.6.2.5 JTAG and TAP Signals DC Specifications .......................................61
5.6.2.6 Serial VID Interface (SVID) DC Specifications................................61
5.6.2.7 Processor Asynchronous Sideband DC Specifications ......................62
5.6.2.8 Miscellaneous Signals DC Specifications........................................62
6 Processor Land Listing .............................................................................................63