User Manual

Signal Descriptions
36 Datasheet
PMSYNC
Power Management Sync. A sideband signal to communicate power
management status from the Platform Controller Hub (PCH) to the
processor.
PROCHOT_N
PROCHOT_N will go active when the processor temperature monitoring
sensor detects that the processor has reached its maximum safe operating
temperature. This indicates that the processor Thermal Control Circuit has
been activated, if enabled. This signal can also be driven to the processor to
activate the Thermal Control Circuit. This signal is sampled after PWRGOOD
assertion.
If PROCHOT_N is asserted at the de-assertion of RESET_N, the processor
will tri-state its outputs.
PWRGOOD
PWRGOOD is a processor input. The processor requires this signal to be a
clean indication that all processor clocks and power supplies are stable and
within their specifications.
"Clean" implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are turned
on until they come within specification. The signal must then transition
monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must
again be stable before a subsequent rising edge of PWRGOOD. PWRGOOD
transitions from inactive to active when all supplies except VCCIN are stable.
The signal must be supplied to the processor; it is used to protect internal
circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
RESET_N
Global reset signal. Asserting the RESET_N signal resets the processor to a
known state and invalidates its internal caches without writing back any of
their contents.
Note: Some PLL, Intel QuickPath Interconnect, and error states are not
affected by reset and only PWRGOOD forces them to a known state.
THERMTRIP_N
Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible
critical over-temperature conditions: One, the processor junction
temperature has reached a level beyond which permanent silicon damage
may occur and Two, the system memory interface has exceeded a critical
temperature limit set by BIOS. Measurement of the processor junction
temperature is accomplished through multiple internal thermal sensors that
are monitored by the Digital Thermal Sensor (DTS). Simultaneously, the
Power Control Unit (PCU) monitors external memory temperatures using the
dedicated SMBus interface to the DIMMs. If any of the DIMMs exceed the
BIOS defined limits, the PCU will signal THERMTRIP_N to prevent damage to
the DIMMs. Once activated, the processor will stop all execution and shut
down all PLLs. To further protect the processor, its core voltage (V
CCIN
),
V
CCD
, V
CCIO_IN
, V
CCPECI
supplies must be removed following the assertion of
THERMTRIP_N. Once activated, THERMTRIP_N remains latched until
RESET_N is asserted. While the assertion of the RESET_N signal may de-
assert THERMTRIP_N, if the processor's junction temperature remains at or
above the trip level, THERMTRIP_N will again be asserted after RESET_N is
de-asserted. This signal can also be asserted if the system memory
interface has exceeded a critical temperature limit set by BIOS.
Table 4-13. Processor Asynchronous Sideband Signals (Sheet 2 of 2)
Signal Name Description