User Manual

Datasheet 35
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Signal Descriptions
4.8 Serial VID Interface (SVID) Signals
4.9 Processor Asynchronous Sideband and
Miscellaneous Signals
TDO
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TMS
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRST_N
TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must
be driven low during power on Reset.
Table 4-12. SVID Signals
Signal Name Description
SVIDALERT_N Serial VID alert.
SVIDCLK Serial VID clock.
SVIDDATA Serial VID data out.
Table 4-13. Processor Asynchronous Sideband Signals (Sheet 1 of 2)
Signal Name Description
CATERR_N
Indicates that the system has experienced a fatal or catastrophic error and
cannot continue to operate. The processor will assert CATERR_N for
unrecoverable machine check errors and other internal unrecoverable
errors. It is expected that every processor in the system will wire-OR
CATERR_N for all processors. Since this is an I/O land, external agents are
allowed to assert this land which will cause the processor to take a machine
check exception. This signal is sampled after PWRGOOD assertion. On the
processor, CATERR_N is used for signaling the following types of errors:
• Legacy MCERR’s, CATERR_N is asserted for 16 BCLKs.
• Legacy IERR’s, CATERR_N remains asserted until warm or cold reset.
ERROR_N[2:0]
Error status signals for integrated I/O (IIO) unit:
• 0 = Hardware correctable error (no operating system or firmware action
necessary)
• 1 = Non-fatal error (operating system or firmware action required to
contain and recover)
• 2 = Fatal error (system reset likely required to recover)
MEM_HOT_C01_N
MEM_HOT_C23_N
Memory throttle control. Signals external BMC-less controller that DIMM is
exceeding temperature limit and needs to increase to max fan speed.
MEM_HOT_C01_N and MEM_HOT_C23_N signals have two modes of
operation - input and output mode.
Input mode is externally asserted and is used to detect external events such
as VR_HOT# from the memory voltage regulator and causes the processor
to throttle the appropriate memory channels.
Output mode is asserted by the processor known as level mode. In level
mode, the output indicates that a particular branch of memory subsystem is
hot.
MEM_HOT_C01_N is used for memory channels 0 & 1 while
MEM_HOT_C23_N is used for memory channels 2 & 3.
MSMI_N
Machine Check Exception (MCE) is signaled via this pin when eMCA2 is
enabled.
Table 4-11. JTAG and TAP Signals (Sheet 2 of 2)
Signal Name Description