User Manual
Datasheet 17
Introduction
Rank
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a DDR4
DIMM.
RDIMM Registered Dual In-line Memory Module
RTID
Request Transaction IDs are credits issued by the Cbo to track outstanding
transaction, and the RTIDs allocated to a Cbo are topology dependent.
SCI System Control Interrupt. Used in ACPI protocol.
SKU
Stock Keeping Unit (SKU) is a subset of a processor type with specific features,
electrical, power and thermal specifications. Not all features are supported on all
SKUs. A SKU is based on specific use condition assumption.
SMBus
System Management Bus. A two-wire interface through which simple system
and power management related devices can communicate with the rest of the
system.
SSE Intel
®
Streaming SIMD Extensions (Intel
®
SSE)
STD Suspend-to-Disk
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to "free air"
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
STR Suspend-to-RAM
SVID Serial Voltage Identification
TAC Thermal Averaging Constant
TCC Thermal Control Circuit
TDP Thermal Design Power
TLP Transaction Layer Packet
TSOD Temperature Sensor On DIMM
UDIMM Unbuffered Dual In-line Memory Module
Uncore
The portion of the processor comprising the shared LLC cache, Cbo, IMC, HA,
PCU, Ubox, IIO and Intel QPI link interface.
Unit Interval
Signaling convention that is binary and unidirectional. In this binary signaling,
one bit is sent for every edge of the forwarded clock, whether it be a rising edge
or a falling edge. If a number of edges are collected at instances t
1
, t
2
, t
n
,....,
t
k
then the UI at instance "n" is defined as: UI
n
= t
n
- t
n-1
V
CCD
DDR power rail
V
CCIN
Primary voltage input to the voltage regulators integrated into the processor.
V
CCIO_IN
IO voltage supply input
VSS Processor ground
x1 Refers to a Link or Port with one Physical Lane
x16 Refers to a Link or Port with sixteen Physical Lanes
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
Table 1-1. Terminology (Sheet 3 of 3)
Term Description