User Manual

Introduction
16 Datasheet
Intel
®
ME Intel
®
Management Engine
Intel
®
QuickData
Technology
Intel QuickData Technology is a platform solution designed to maximize the
throughput of server data traffic across a broader range of configurations and
server environments to achieve faster, scalable, and more reliable I/O.
Intel
®
QuickPath
Interconnect (Intel
®
QPI)
A cache-coherent, link-based Interconnect specification for Intel processors,
chipsets, and I/O bridge components.
Intel
®
Turbo Bo o s t
Technology
A feature that opportunistically enables the processor to run a faster frequency.
This results in increased performance of both single and multi-threaded
applications.
Intel
®
TXT Intel
®
Trusted Execution Technology
Intel
®
Virtualization
Technology (Intel
®
VT)
Processor Virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
Intel
®
VT-d
Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or operating
system) control, for enabling I/O device Virtualization. Intel VT-d also brings
robust security by providing protection from errant DMAs by using DMA
remapping, a key feature of Intel VT-d.
IOV I/O Virtualization
IQ Instruction Queue. Part of the core architecture.
IVR
Integrated Voltage Regulation (IVR): The processor supports several integrated
voltage regulators.
Jitter
Any timing variation of a transition edge or edges from the defined Unit Interval
(UI).
LGA2011-v3 Socket
The 2011-v3 land FC-LGA package mates with the system board through this
surface mount, 2011-v3 contact socket.
LLC Last Level Cache
LRDIMM Load Reduced Dual In-line Memory Module
LRU Least Recently Used. A term used in conjunction with cache allocation policy.
MESIF
Modified/Exclusive/Shared/Invalid/Forwarded. States used in conjunction with
cache coherency
MLC Mid Level Cache
NCTF
Non-Critical to Function: NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
PCH
Platform Controller Hub. The next generation chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCI Express 2.0 PCI Express Generation 2.0
PCI Express 3.0
The third generation PCI Express specification that operates at twice the speed
of PCI Express 2.0 (8 Gb/s); PCI Express 3.0 is completely backward compatible
with PCI Express 1.0 and 2.0.
PECI Platform Environment Control Interface
Processor Includes the 64-bit cores, uncore, I/Os, and package
Processor Core
The term "processor core" refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
R3QPI
Intel QPI Agent. An internal logic block providing interface between internal Ring
and external Intel QPI.
Table 1-1. Terminology (Sheet 2 of 3)
Term Description