Datasheet

Signal Quality
Data transfer requires the clean reception of data signals and clock signals. Ringing
below receiver thresholds, non-monotonic signal edges, and excessive voltage swings
will adversely affect system timings. Ringback and signal non-monotonicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines.
Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate
oxide integrity, and can cause device failure if absolute voltage limits are exceeded.
Overshoot and undershoot can also cause timing degradation due to the build up of
inter-symbol interference (ISI) effects.
For these reasons, it is crucial that the designer work towards a solution that provides
acceptable signal quality across all systematic variations encountered in volume
manufacturing.
This section documents signal quality metrics used to derive topology and routing
guidelines through simulation. All specifications are specified at the processor die (pad
measurements).
Specifications for signal quality are for measurements at the processor core only and
are only observable through simulation. Therefore, proper simulation is the only way
to verify proper timing and signal quality.
DDR Signal Quality Specifications
Overshoot (or undershoot) is the absolute value of the maximum voltage above or
below VSS. The overshoot/undershoot specifications limit transitions beyond specified
maximum voltages or VSS due to the fast signal edge rates. The processor can be
damaged by single and/or repeated overshoot or undershoot events on any input,
output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great
enough). Baseboard designs which meet signal integrity and timing requirements and
which do not exceed the maximum overshoot or undershoot limits listed in Table 17
on page 45 will ensure reliable IO performance for the lifetime of the processor.
I/O Signal Quality Specifications
Signal Quality specifications for PCIe* Signals are included as part of the PCIe DC
specifications.
Input Reference Clock Signal Quality Specifications
Overshoot/Undershoot and Ringback specifications for BCLK{0/1}_D[N/P] are found in
Table 17 on page 45. Overshoot/Undershoot and Ringback specifications for the
DDR4 Reference Clocks are specified by the DIMM.
Overshoot/Undershoot Tolerance
Overshoot (or undershoot) is the absolute value of the maximum voltage above or
below VSS, see Figure 11 on page 46. The overshoot/undershoot specifications limit
transitions beyond VCCD or VSS due to the fast signal edge rates. The processor can
be damaged by single and/or repeated overshoot or undershoot events on any input,
output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great
enough). Baseboard designs which meet signal integrity and timing requirements and
which do not exceed the maximum overshoot or undershoot limits listed in the
following table will insure reliable IO performance for the lifetime of the processor.
2.11
2.11.1
2.11.2
2.11.3
2.11.4
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical
Datasheet September 2014
44 Order No.: 330783-001