Datasheet

DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted.
DC specifications are only valid while meeting specifications for case temperature
(TCASE specified in the Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product
Families Thermal/Mechanical Specification and Design Guide (TMSDG)), clock
frequency, and input voltages. Care should be taken to read all notes associated with
each specification.
Voltage and Current Specifications
Table 13. Voltage Specification
Symbols Parameter Voltage
Plane
Min Nom Max Unit Notes
1
V
CCIN
Input to
Integrated
Voltage
Regulator
(Launch - FMB)
V
CCIN
1.47 1.82 1.85 V 2, 3, 4, 5,
8, 10, 13
V
VID_STEP
(V
CCIN
, V
CCD
)
VID step size
during a
transition
10.0 mV 6
V
CCD (
V
CCD_01,
V
CCD_23)
I/O Voltage for
DDR4
(Standard
Voltage)
V
CCD
0.97*V
CCD_NOM
1.2 1.044*V
CCD_NOM
V 7, 9, 10,
11, 12
Note:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on final
characterization.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is
required.
3. The V
CCIN
voltage specification requirements are measured across the remote sense pin pairs (V
CCIN_SENSE
and
V
SS_VCCIN_SENSE
) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 MΩ
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external
noise from the system is not coupled in the scope probe.
4. Refer to Table 15 on page 33 and corresponding Figure 4 on page 35. The processor should not be subjected to any
static V
CCIN
level that exceeds the V
CCIN_MAX
associated with any particular current. Failure to adhere to this specification
can shorten processor lifetime.
5. Minimum V
CCIN
and maximum I
CCIN
are specified at the maximum processor case temperature (T
CASE
) shown in the Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families Thermal/Mechanical Specification and Design Guide (TMSDG).
I
CCIN_MAX
is specified at the relative V
CC_MAX
point on the V
CCIN
load line. The processor is capable of drawing I
CCIN_MAX
for
up to 4 ms.
6. This specification represents the V
CCIN
reduction or V
CCIN
increase due to each VID transition. For Voltage Identification
(VID) see Voltage Identification (VID) on page 17. AC timing requirements for VID transitions are included in Figure 3 on
page 32.
7. Baseboard bandwidth is limited to 20 MHz.
8. FMB is the flexible motherboard guidelines. See Flexible Motherboard Guidelines (FMB) on page 29 for details.
9. DC + AC + Ripple = Total Tolerance
10.For SVID Power State Functions (SetPS) see SVID Power State Functions: SetPS on page 19.
11.V
CCD
tolerance at processor pins. Required in order to meet +/-5% tolerance at processor die.
12.The V
CCD01
, V
CCD23
voltage specification requirements are measured across vias on the platform. Choose V
CCD01
or V
CCD23
vias close to the socket and measure with a DC to 100MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model
oscilloscopes), using 1.5 pF maximum probe capacitance, and 1M ohm minimum impedance. The maximum length of the
ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope
probe.
13.V
CCIN
has a V
boot
setting of 0.0V and is not included in the PWRGOOD indication.
2.9
2.9.1
Electrical Specifications—Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical
September 2014 Datasheet
Order No.: 330783-001 31