Datasheet

Output Tri-State Signal Groups Signals
QPI1_DTX_DP[19:00]
PCI Express* PE1A_TX_DN[3:0]
PE1A_TX_DP[3:0]
PE1B_TX_DN[7:4]
PE1B_TX_DP[7:4]
PE2A_TX_DN[3:0]
PE2A_TX_DP[3:0]
PE2B_TX_DN[7:4]
PE2B_TX_DP[7:4]
PE2C_TX_DN[11:8]
PE2C_TX_DP[11:8]
PE2D_TX_DN[15:12]
PE2D_TX_DP[15:12]
PE3A_TX_DN[3:0]
PE3A_TX_DP[3:0]
PE3B_TX_DN[7:4]
PE3B_TX_DP[7:4]
PE3C_TX_DN[11:8]
PE3C_TX_DP[11:8]
PE3D_TX_DN[15:12]
PE3D_TX_DP[15:12]
PE_HP_SCL
PE_HP_SDA
DMI2 DMI_TX_DN[3:0]
DMI_TX_DP[3:0]
SMBus DDR_SCL_C01
DDR_SDA_C01
DDR_SCL_C23
DDR_SDA_C23
Processor Sideband CATERR_N
ERROR_N[2:0]
BPM_N[7:0]
PRDY_N
THERMTRIP_N
PROCHOT_N
PECI
MEM_HOT_C01_N
MEM_HOT_C23_N
PM_FAST_WAKE_N
FIVR_FAULT
SVID SVIDCLK
SVIDDATA
Mixing Processors
Intel supports and validates two configurations only in which all processors operate
with the same Intel
®
QuickPath Interconnect frequency, core frequency, power
segment, and have the same internal cache sizes. Mixing components operating at
different internal clock frequencies is not supported and will not be validated by Intel.
Combining processors from different power segments is also not supported.
2.6
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical
Datasheet September 2014
28 Order No.: 330783-001