Datasheet

Differential/Single Ended Buffer Type Signal
CMOS 1.05V Input EAR_N
Output SKTOCC_N
Power/Other Signals
Power / Ground V
CCIN
, V
CCD_01
, V
CCD_23
, V
CCIO_IN
,
V
CCPECI
, V
SS
Sense Points VCCIN_SENSE
VSS_VCCIN_SENSE
Note:
1. Refer to "Signal Descriptions" for signal description details.
2. DDR{0/1/2/3} refers to DDR4 Channel 0, DDR4 Channel 1, DDR4 Channel 2 and DDR4 Channel 3.
Table 8. Signals with On-Die Weak PU/PD
Signal Name Pull Up/Pull Down Rail Value Units
BIST_ENABLE Pull Up VCCIO_IN 5K-15K Ω
BMCINIT Pull Down VSS 5K-15K Ω
DEBUG_EN_N Pull Up VCCIO_IN 5K-15K Ω
EAR_N Pull Up VCCIO_IN 5K-15K Ω
FRMAGENT Pull Down VSS 5K-15K Ω
PM_FAST_WAKE_N Pull Up VCCIO_IN 5K-15K Ω
PREQ_N Pull Up VCCIO_IN 5K-15K Ω
SAFE_MODE_BOOT Pull Down VSS 5K-15K Ω
SOCKET_ID[1:0] Pull Down VSS 5K-15K Ω
TCK Pull Down VSS 5K-15K Ω
TDI Pull Up VCCIO_IN 5K-15K Ω
TMS Pull Up VCCIO_IN 5K-15K Ω
TRST_N Pull Up VCCIO_IN 5K-15K Ω
TXT_AGENT Pull Down VSS 5K-15K Ω
TXT_PLTEN Pull Up VCCIO_IN 5K-15K Ω
Power-On Configuration (POC) Options
Several configuration options can be configured by hardware. The processor samples
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, please refer to the table below.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
2.4
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical
Datasheet September 2014
26 Order No.: 330783-001