Datasheet

Document Document Number/Location
Intel
®
64 and IA-32 Architectures Optimization Reference Manual
Intel
®
Virtualization Technology Specification for Directed I/O
Architecture Specification
http://www.intel.com/
content/www/us/en/intelligent-
systems/intel-technology/vt-
directed-io-spec.html
Intel
®
Trusted Execution Technology Software Development Guide http://www.intel.com/technology/
security/
Terminology
Term Description
ASPM Active State Power Management
BMC Baseboard Management Controller
Cbo Caching Agent (also referred to as CA). It is a term used for the
internal logic providing ring interface to LLC and Core. The Cbo is a
functional unit in the processor. A Caching Agent is defined per the
RS - Intel
®
QuickPath Interconnect External Link Specification.
DDR4 Fourth generation Double Data Rate SDRAM memory technology.
DMA Direct Memory Access
DMI2 Direct Media Interface Gen2 operating at PCI Express 2.0 speed.
DSB Data Stream Buffer. Part of the processor core architecture.
DTLB Data Translation Look-aside Buffer. Part of the processor core
architecture.
DTS Digital Thermal Sensor
ECC Error Correction Code
Enhanced Intel SpeedStep
®
Technology
Allows the operating system to reduce power consumption when
performance is not needed.
Execute Disable Bit The Execute Disable bit allows memory to be marked as executable
or non-executable, when combined with a supporting operating
system. If code attempts to run in non-executable memory the
processor raises an error to the operating system. This feature can
prevent some classes of viruses or worms that exploit buffer
overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel
®
64 and IA-32 Architectures
Software Developer's Manuals for more detailed information.
FLIT Flow Control Unit. The Intel QPI Link layer's unit of transfer; 1 Flit =
80-bits.
Functional Operation Refers to the normal operating conditions in which all processor
specifications, including DC, system bus, signal quality, mechanical,
and thermal, are satisfied.
GSSE Extension of the SSE/SSE2 (Streaming SIMD Extensions) floating
point instruction set to 256b operands.
HA A Home Agent (HA) orders read and write requests to a piece of
coherent memory.
ICU Instruction Cache Unit. Part of the processor core architecture.
IFU Instruction Fetch Unit. Part of the processor core.
continued...
1.1.3
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families—Introduction
Intel
®
Xeon
®
Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical
Datasheet September 2014
10 Order No.: 330783-001