Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical Datasheet September 2014 Order No.
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Revision History—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Revision History Document Number 330783 Revision Number 001 September 2014 Order No.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Contents Contents Revision History..................................................................................................................3 1.0 Introduction................................................................................................................. 8 1.1 Electrical Datasheet Introduction.............................................................................. 8 1.1.1 Structure and Scope.......................
Contents—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families 4.6 System Reference Clock Signals..............................................................................52 4.7 JTAG and TAP Signals............................................................................................53 4.8 Serial VID Interface (SVID) Signals......................................................................... 53 4.9 Processor Asynchronous Sideband and Miscellaneous Signals............................
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Figures Figures 1 2 3 4 5 6 7 8 9 10 11 Input Device Hysteresis............................................................................................15 VR Power State Transitions....................................................................................... 20 Serial VID Interface (SVID) Signals Clock Timings........................................................32 VCCIN Static and Transient Tolerance Loadlines..................
Tables—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Structure of the Processor Datasheet........................................................................... 9 Public Publications..................................................................................................... 9 Power and Ground Lands....................................................................................
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Introduction 1.0 Introduction The Datasheet provides descriptions of the Intel® Xeon® processor v3 product families registers and Electrical specifications (including DC electrical specifications, signal integrity, and land and signal definitions). This document is distributed as a part of the complete Datasheet consisting of two volumes.
Introduction—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families 1.1.1 Structure and Scope The following table summarizes the structure and scope of each volume of the processor Datasheet. Table 1. Structure of the Processor Datasheet Volume One: Electrical Datasheet • Introduction • Electrical Specifications • Processor Land Listing • Processor Signal Descriptions Volume Two: Register Information 1.1.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Introduction Document Intel® 1.1.3 Document Number/Location 64 and IA-32 Architectures Optimization Reference Manual Intel® Virtualization Technology Specification for Directed I/O Architecture Specification http://www.intel.com/ content/www/us/en/intelligentsystems/intel-technology/vtdirected-io-spec.html Intel® Trusted Execution Technology Software Development Guide http://www.intel.
Introduction—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Term Description IIO The Integrated I/O Controller. An I/O controller that is integrated in the processor die. IMC The Integrated Memory Controller. A Memory Controller that is integrated in the processor die. IQ Instruction Queue. Part of the core architecture.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Introduction Term Description NID Node ID (NID) or NodeID (NID). The processor implements up to 4bits of NodeID (NID). NodeID Node ID (NID) or NodeID (NID). pcode Pcode is microcode which is run on the dedicated microcontroller within the PCU. PCH Platform Controller Hub.
Introduction—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Term 1.1.4 Description TSOD Temperature Sensor On DIMM UDIMM Unbuffered Dual In-line Memory Module Uncore The portion of the processor comprising the shared LLC cache, Cbo, IMC, HA, PCU, Ubox, IIO and Intel QPI link interface. Unit Interval Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications 2.0 Electrical Specifications This chapter describes processor signaling, DC specifications, and signal quality. References to various interfaces (memory, PCIe*, Intel QPI, PECI, etc.) are also described. 2.1 Integrated Voltage Regulation A new feature to the processor is the integration of platform voltage regulators into the processor.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families 2.2.3 DMI2/PCI Express Signals The Direct Media Interface Gen 2 (DMI2) sends and receives packets and/or commands to the PCH. The DMI2 is an extension of the standard PCI Express Specification. The DMI2/PCI Express Signals consist of DMI2 receive and transmit input/output signals and a control signal to select DMI2 or PCIe* 2.0 operation for port 0. Please refer to Table 7 on page 23 for further details. 2.2.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications 2.2.6 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) The processor Core, processor Uncore, Intel® QuickPath Interconnect link, PCI Express* and DDR4 memory interface frequencies) are generated from BCLK{0/1}_DP and BCLK{0/1}_DN signals. There is no direct link between core frequency and Intel QuickPath Interconnect link frequency (e.g., no core frequency to Intel QuickPath Interconnect multiplier).
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families 2.2.9 Power, Ground and Sense Signals Processors also include various other signals, including power / ground and sense points. Details can be found in Table 7 on page 23. Power and Ground Lands All VCCD, VCCIN, and VCCIO_IN, and VCCPECI lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications The processor uses voltage identification signals to support automatic selection of VCCIN power supply voltage. If the processor socket is empty (SKTOCC_N high), or a "not supported" response is received from the SVID bus, then the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself or not power on.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families SetVID Decay The SetVID_Decay command is the slowest of the DVID transitions. It is normally used for VID down transitions. The VR does not control the slew rate, the output voltage declines with the output load current only. The SetVID_Decay command is preemptive, the VR interrupts its current processes and moves to the new VID.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Figure 2. VR Power State Transitions PS0 PS1 PS2 SVID Voltage Rail Addressing The processor addresses 3 different voltage rail control segments within VR12.5 (VCCIN, VCCD_01, and VCCD_23). The SVID data packet contains a 4-bit addressing code: Table 4.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families PWM Address (HEX) 4. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not used. Table 5. VR12.5 Reference Code Voltage Identification (VID) Table HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN 00 0.00 55 1.34 78 1.69 9B 2.04 BE 2.39 E1 2.74 33 1.00 56 1.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN 52 1.31 75 1.66 98 2.01 BB 2.36 DE 2.71 53 1.320 76 1.67 99 2.02 BC 2.37 DF 2.72 54 1.33 77 1.68 9A 2.03 BD 2.38 E0 2.73 HEX VCCIN Note: 1. 00h = Off State 2. VID Range HEX 01-32 are not used by the Intel® Xeon® processor E5-1600 and E5-2600 v3 product families 3. For VID Ranges supported see Table 13 on page 31 4.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Table 6. Signal Description Buffer Types Signal Description Analog Analog reference or output. May be used as a threshold voltage or for buffer compensation Asynchronous1 Signal has no timing relationship with any system reference clock. CMOS CMOS buffers: 1.05V DDR4 buffers: 1.2V DMI2 Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express* 2.0 and 1.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Differential/Single Ended Buffer Type Signal DDR4 Data Signals Differential SSTL Input/Output DDR{0/1/2/3}_DQS_D[N/P] [17:0] Single ended SSTL Input/Output DDR{0/1/2/3}_DQ[63:0] DDR{0/1/2/3}_ECC[7:0] SSTL Input DDR{0/1/2/3}_ALERT_N CMOS Input DRAM_PWR_OK_C01 DRAM_PWR_OK_C23 DDR4 Miscellaneous Signals Single ended Note: Input voltage from platform cannot exceed 1.08V max. CMOS 1.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Differential/Single Ended Buffer Type Intel® Differential QPI Input Intel® QPI Output Signal QPI{0/1}_DRX_D[N/P][19:0] QPI{0/1}_CLKRX_D[N/P] QPI{0/1}_DTX_D[N/P][19:0] QPI{0/1}_CLKTX_D[N/P] Platform Environmental Control Interface (PECI) Single ended PECI Input/Output PECI System Reference Clock (BCLK{0/1}) Differential CMOS 1.05V Input BCLK{0/1}_D[N/P] CMOS 1.05V Input TCK TDI TMS TRST_N CMOS 1.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Differential/Single Ended Buffer Type Signal CMOS 1.05V Input EAR_N Output SKTOCC_N Power / Ground VCCIN, VCCD_01, VCCD_23, VCCIO_IN, VCCPECI, VSS Sense Points VCCIN_SENSE VSS_VCCIN_SENSE Power/Other Signals Note: 1. Refer to "Signal Descriptions" for signal description details. 2. DDR{0/1/2/3} refers to DDR4 Channel 0, DDR4 Channel 1, DDR4 Channel 2 and DDR4 Channel 3. Table 8.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Table 9.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Output Tri-State Signal Groups Signals QPI1_DTX_DP[19:00] 2.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Note: All processors within a system must run at a common maximum non-Turbo ratio. The system BIOS may be required to program the FLEX_RATIO register if mixed frequency processors are populated. Not all operating systems can support dual processors with mixed frequencies.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Symbol Parameter Min Max Unit 2. Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Overshoot/ Undershoot Tolerance on page 44. Excessive Overshoot or undershoot on any signal will likely result in permanent damage to the processor.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families DC Specifications 2.9 DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (TCASE specified in the Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Thermal/Mechanical Specification and Design Guide (TMSDG)), clock frequency, and input voltages.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Figure 3. Serial VID Interface (SVID) Signals Clock Timings SVIDCLK@ cpu pad Tco SVIDDATA(drive) @ cpu pad valid TSetup valid SVIDDATA (combine dr&rcv ) @ cpu pad Freque ncy Optimiz ed 135W 0.8 (2.2) 0.8 (2.2) 288 290 2, 4 175 0.1 0.001 1.4 (2.45) 1.4 (2.45) 82 0.02 0.001 0.8 (2.2) 0.8 (2.2) 267 270 2, 4 189 0.1 0.001 1.4 (2.45) 1.4 (2.45) 88 0.02 0.001 0.8 (2.2) 0.8 (2.
0.02 0.001 0.8 (2.2) 0.8 (2.2) 168 170 2,4 Basic 105 0.1 0.001 1.4 (2.45) 1.4 (2.45) 50 0.02 0.001 0.8 (2.2) 0.8 (2.2) 168 170 2, 4 83 0.1 0.001 1.4 (2.45) 1.4 (2.45) 40 0.02 0.001 0.8 (2.2) 0.8 (2.2) 127 130 2, 4 70 0.1 0.001 1.4 (2.45) 1.4 (2.45) 34 0.02 0.001 0.8 (2.2) 0.8 (2.2) 107 110 2, 4 156 0.1 0.001 1.4 (2.45) 1.4 (2.45) 73 0.02 0.001 0.8 (2.2) 0.8 (2.2) 238 240 2, 4 136 0.1 0.001 1.4 (2.45) 1.4 (2.45) 64 0.02 0.001 0.8 (2.2) 0.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications ICCIN (A) VCCIN_Max (V) VCCIN_Nom (V) VCCIN_Min (V) 50 VID - 0.031 VID - 0.053 VID - 0.075 60 VID - 0.041 VID - 0.063 VID - 0.085 70 VID - 0.052 VID - 0.074 VID - 0.096 80 VID - 0.062 VID - 0.084 VID - 0.106 90 VID - 0.073 VID - 0.095 VID - 0.117 100 VID - 0.083 VID - 0.105 VID - 0.127 110 VID - 0.094 VID - 0.116 VID - 0.138 120 VID - 0.104 VID - 0.126 VID - 0.148 130 VID - 0.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Figure 4. VCCIN Static and Transient Tolerance Loadlines VccIN normalized droop (V) (Offset fom measured sVID) 2.9.2 0.040 0.020 0.000 -0.020 -0.040 -0.060 -0.080 -0.100 -0.120 -0.140 -0.160 -0.180 -0.200 -0.220 -0.240 -0.260 -0.280 230 220 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 VccIN load (A) VccIN_Max (V) VccIN_Typ (V) VccIN_Min (V) 1.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Figure 5. VCCIN Overshoot Example Waveform VOS_MAX Voltage [V] VID+ +VOS_MAX VOS_MAX VCCIN_MAX VCCIN_MAX VCCIN_MAX (I1) TOS_MAX 0 5 10 15 20 25 30 Time [us] Note: 1. VOS_MAX is the measured overshoot voltage above VCCIN_MAX. 2. TOS_MAX is the measured time duration above VCCIN_MAX. 3. VCCIN_MAX = VID + TOB 2.9.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Symbol Parameter Min Nom VOL Output Low Voltage Varies VOH Output High Voltage VCCD Max Notes1 Units 10 Reference Clock Signal R ON DDR4 Clock Buffer On Resistance 27 33 ohm 6 16 20 ohm 6 ohm 6 V 1, 2 V 1, 2 33 ohm 6 99 ohm 304 mV 2, 3 mV 2, 4, 5 Command Signals R ON R ON DDR4 Command Buffer On Resistance DDR4 Reset Buffer On Resistance 78 VOL_CMOS1.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications 2.9.3.2 Symbol PECI DC Specifications Definition and Conditions Min Max Units VIn Input Voltage Range -0.150 VHysteresis Hysteresis 0.100 * VCCPECI VN Negative-edge threshold voltage 0.275 * VCCPECI 0.500 * VCCPECI V Figure 1 on page 15 2 VP Positive-edge threshold voltage 0.550 * VCCPECI 0.725 * VCCPECI V Figure 1 on page 15 2 I Pullup Resistance (VOH = 0.75 * VCCPECI) -6.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Symbol Vcross (rel) Parameter Signal Relative Crossing Point Single Ended ΔVcross Range of Crossing Points VTH Min Max Unit Figure Notes1 0.250 + 0.5*(VH - 0.700) 0.550 + 0.5*(VH - 0.700) V avg Figure 7 on page 40 3, 4, 5, 9 avg Single Ended N/A 0.140 V Figure 9 on page 40 6, 9 Threshold Voltage Single Ended Vcross - 0.1 Vcross + 0.1 V 9 IIL Input Leakage Current N/A 1.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Figure 7. BCLK{0/1} Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 550 + 0.5 (VHavg - 700) 450 400 250 + 0.5 (VHavg - 700) 350 300 250 mV 250 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 8. BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point and Swing VMAX = 1.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Symbol IL Parameter Min Max Units Leakage Current Signals 50 200 µA Output Edge Rate (50 ohm to VCCIO_IN, between VIL and VIH) 0.05 0.6 V/ns Notes 1 Note: 1. Value obtained through test bench with 50Ω pull up to VCCIO_IN. 2.9.3.5 JTAG and TAP Signals DC Specifications Symbol Parameter Min Max 0.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications 2.9.3.7 Processor Asynchronous Sideband DC Specifications Symbol Parameter Min Max Units Notes V 1, 2 V 1, 2 200 µA 1,2 CMOS1.05v Signals VIL_CMOS1.05V Input Low Voltage 0.4*V VIH_CMOS1.05V Input High Voltage 0.6*V IIL_CMOS1.05V Input Leakage Current 50 CCIO_IN CCIO_IN Open Drain CMOS (ODCMOS) Signals VIL_ODCMOS Input Low Voltage Signals: CATERR_N, MSMI_N, PM_FAST_WAKE_N 0.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Segment Segment Optimized Workstation Frequency Optimized Advanced Server Standard Server Basic Low Power Embedded Model Number TDP C1E (W) 2 C3 (W) 2 C6 (W) E5-2699 v3 145W 18-Core 56 36 14 E5-2698 v3 135W 16-Core 47 33 14 E5-2697 v3 145W 14-Core 45 34 14 E5-2695 v3 120W 14-Core 46 34 14 E5-2683 v3 120W 14-Core 55 38 20 E5-2687 v3 160W 10-Core 41 31 13 E5-1680 v3 140W 8-Co
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications 2.11 Signal Quality Data transfer requires the clean reception of data signals and clock signals. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swings will adversely affect system timings. Ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Table 17. Processor I/O Overshoot/Undershoot Specifications Signal Group Maximum Undershoot Maximum Overshoot Overshoot Duration Undershoot Duration Notes Intel QuickPath Interconnect -0.2 * VCCIO_IN 1.2 * VCCIO_IN 39 ps 15 ps 1, 2 DDR4 -0.22*VCCD 1.22*VCCD 0.25*TCH 0.1*TCH 1, 2, 3 Processor Asynchronous Sideband Signals -0.35 * VCCIO_IN 1.35 * VCCIO_IN 1.25 ns 0.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications Overshoot/Undershoot Pulse Duration Pulse duration describes the total amount of time that an overshoot/undershoot event exceeds the overshoot/undershoot reference voltage. The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Reading Overshoot/Undershoot Specification Tables The overshoot/undershoot specification for the processor is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot and the activity factor (AF).
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Processor Land Listing 3.0 Processor Land Listing Refer to Appendix A in this document. Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical Datasheet 48 September 2014 Order No.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families 4.0 Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions This chapter describes the Intel® Xeon® processor E5-1600 and E5-2600 v3 product families signals. They are arranged in functional groups according to their associated interface or category. 4.1 System Memory Interface Table 19.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions Signal Name Table 20. Description DDR{0/1/2/3}_ODT[5:0] On Die Termination. Enables DRAM on die termination during Data Write or Data Read transactions. DDR{0/1/2/3}_RAS_N Row Address Strobe. MUXed with DDR{0/1/2/3}_MA[16]. DDR{0/1/2/3}_WE_N Write Enable. MUXed with DDR{0/1/2/3}_MA[14].
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Name Table 23.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions 4.3 DMI2/PCI Express Port 0 Signals Table 25. DMI2 and PCI Express Port 0 Signals Signal Name Description DMI_RX_DN[3:0] DMI_RX_DP[3:0] DMI2 Receive Data Input DMI_TX_DP[3:0] DMI_TX_DN[3:0] DMI2 Transmit Data Output 4.4 Intel® QuickPath Interconnect Signals Table 26.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families 4.7 JTAG and TAP Signals Table 29. JTAG and TAP Signals Signal Name Description BPM_N[7:0] Breakpoint and Performance Monitor Signals: I/O signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. These are 100 MHz signals.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions Signal Name Description • • • 0 = Hardware correctable error (no operating system or firmware action necessary) 1 = Non-fatal error (operating system or firmware action required to contain and recover) 2 = Fatal error (system reset likely required to recover) MEM_HOT_C01_N MEM_HOT_C23_N Memory throttle control.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Name Table 32. Description PWRGOOD PWRGOOD is a processor input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions Signal Name Description This signal is pulled down on the die, refer to Table 8 on page 26 for details. EAR_N External Alignment of Reset, used to bring the processor up into a deterministic state. This signal is pulled up on the die, refer to Table 8 on page 26 for details.
Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families Signal Name Description 1 = Default. The platform is Intel TXT enabled. All sockets should be set to one. In a non-Scalable DP platform this is the default. When this is set, Intel TXT functionality requires user to explicitly enable Intel TXT via BIOS setup. This signal is pulled up on the die, refer to Table 8 on page 26 for details. 4.
Appendix A: Pin List Appendix A: Pin List September 2014 Order No: 330783-001 Intel(R) Xeon(R) Processor E5-1600 and E5-2600 v3 Product Families, Vol.
Appendix A: Pin List Pin Name BCLK0_DN BCLK0_DP BCLK1_DN BCLK1_DP BIST_ENABLE BMCINIT BPM_N[0] BPM_N[1] BPM_N[2] BPM_N[3] BPM_N[4] BPM_N[5] BPM_N[6] BPM_N[7] CATERR_N DDR_RESET_C01_N DDR_RESET_C23_N DDR_SCL_C01 DDR_SCL_C23 DDR_SDA_C01 DDR_SDA_C23 DDR0_ACT_N DDR0_ALERT_N DDR0_BA[0] DDR0_BA[1] DDR0_BG[0] DDR0_BG[1] DDR0_CID[2] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CKE[4] DDR0_CKE[5] DDR0_CLK_DN[0] DDR0_CLK_DN[1] DDR0_CLK_DN[2] DDR0_CLK_DN[3] DDR0_CLK_DP[0] DDR0_CLK_DP[1] DDR0_CLK_DP[2] DDR0_CL
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR0_CS_N[3]/CID[1] DDR0_CS_N[4] DDR0_CS_N[5] DDR0_CS_N[6]/CID[3] DDR0_CS_N[7]/CID[4] DDR0_CS_N[8] CC25 CK22 CH24 CH26 CD26 CK24 CK26 BU7 BT6 BW13 BY14 BT14 BU15 CA11 BY12 CE9 CF8 CK10 CJ11 CA9 CD10 CE11 CK8 CJ9 CE13 CG15 CM14 CH14 CC13 CD14 CB8 CM12 CL13 CK28 CH28 CK32 CH32 CL27 CJ27 CL31 CJ31 BT8 CD28 CB28 CD32 SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SS
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47] DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[5] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[6] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQS_DN[0] DDR0_DQS_DN[1] CB32 CE27 CC27 CE31 CC31 CE35 CC35 BU9 CE39 CC39 CF34 CD34 CF38 CD38 CL35 CJ35 CL39 CJ39 CA7 CM34 CK34 CM3
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR0_DQS_DP[1] DDR0_DQS_DP[10] DDR0_DQS_DP[11] DDR0_DQS_DP[12] DDR0_DQS_DP[13] DDR0_DQS_DP[14] DDR0_DQS_DP[15] DDR0_DQS_DP[16] DDR0_DQS_DP[17] DDR0_DQS_DP[2] DDR0_DQS_DP[3] DDR0_DQS_DP[4] DDR0_DQS_DP[5] DDR0_DQS_DP[6] DDR0_DQS_DP[7] DDR0_DQS_DP[8] DDR0_DQS_DP[9] DDR0_ECC[0] DDR0_ECC[1] DDR0_ECC[2] DDR0_ECC[3] DDR0_ECC[4] DDR0_ECC[5] DDR0_ECC[6] DDR0_ECC[7] DDR0_MA[0] DDR0_MA[1] DDR0_MA[10] DDR0_MA[11] DDR0_MA[12] DDR0_MA[13] DDR0_MA[14] DDR
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR0_ODT[2] DDR0_ODT[3] DDR0_ODT[4] DDR0_ODT[5] DDR0_PAR DDR01_VREF DDR1_ACT_N DDR1_ALERT_N CJ23 CC23 CF24 CE25 CK20 BY16 CT16 CR15 CW23 CV22 CV16 CP16 CR25 DA17 DC17 DD16 DF16 CY16 DA15 DC21 DD18 DD20 DC19 DE21 DF18 DF20 DE19 DF22 DE23 CT26 CP26 DA23 DD24 CY26 CV26 DF24 DF26 BV4 BU1 CL5 CM4 CE5 CF6 CK6 CL3 SSTL SSTL SSTL SSTL SSTL DC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[2] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[3] DDR1_DQ[30] DDR1_DQ[31] DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] CR3 CV2 CT6 CP6 CA3 CR1 CP2 CU5 CR5 DA7 DB8 DE11 DC11 DA5 CY6 CB4 DE9 DF10 CT28 CP28 CT32 CP32 CU27 CR27 CU31 CR31 BT4 DA29 DB30 DC33 DF34 DB28 CY28 DA33 DE33 CU35 CR35 BT2 CU39 CR3
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[6] DDR1_DQ[60] DF36 DC39 DA39 CA1 DC35 DB36 DF38 DE39 BY2 CE3 CF4 BW3 CH6 CG3 CU3 DD8 CR29 CY32 CT36 DE37 CY14 CV4 DC9 CV30 DB32 CU37 DA37 DA13 BW1 BY4 CJ5 CH4 CW3 DC7 CU29 DA31 CV36 DD36 CW13 CT4 DB10 CT30 DD32 CR37 DB38 SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL S
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR1_DQS_DP[8] DDR1_DQS_DP[9] DDR1_ECC[0] DDR1_ECC[1] DDR1_ECC[2] DDR1_ECC[3] DDR1_ECC[4] DDR1_ECC[5] DDR1_ECC[6] DDR1_ECC[7] DDR1_MA[0] DDR1_MA[1] DDR1_MA[10] DDR1_MA[11] DDR1_MA[12] DDR1_MA[13] DDR1_MA[14] DDR1_MA[15] DDR1_MA[16] DDR1_MA[17] DDR1_MA[2] DDR1_MA[3] DDR1_MA[4] DDR1_MA[5] DDR1_MA[6] DDR1_MA[7] DDR1_MA[8] DDR1_MA[9] DDR1_ODT[0] DDR1_ODT[1] DDR1_ODT[2] DDR1_ODT[3] DDR1_ODT[4] DDR1_ODT[5] DDR1_PAR DDR2_ACT_N DDR2_ALERT_N DB14 B
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR2_CKE[3] DDR2_CKE[4] DDR2_CKE[5] DDR2_CLK_DN[0] DDR2_CLK_DN[1] DDR2_CLK_DN[2] DDR2_CLK_DN[3] DDR2_CLK_DP[0] DDR2_CLK_DP[1] DDR2_CLK_DP[2] DDR2_CLK_DP[3] DDR2_CS_N[0] DDR2_CS_N[1] DDR2_CS_N[2]/CID[0] DDR2_CS_N[3]/CID[1] DDR2_CS_N[4] DDR2_CS_N[5] DDR2_CS_N[6]/CID[3] DDR2_CS_N[7]/CID[4] DDR2_CS_N[8] DDR2_CS_N[9] DDR2_DQ[0] DDR2_DQ[1] DDR2_DQ[10] DDR2_DQ[11] DDR2_DQ[12] DDR2_DQ[13] DDR2_DQ[14] DDR2_DQ[15] DDR2_DQ[16] DDR2_DQ[17] DDR2_DQ[18]
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR2_DQ[30] DDR2_DQ[31] DDR2_DQ[32] DDR2_DQ[33] DDR2_DQ[34] DDR2_DQ[35] DDR2_DQ[36] DDR2_DQ[37] DDR2_DQ[38] DDR2_DQ[39] DDR2_DQ[4] DDR2_DQ[40] DDR2_DQ[41] DDR2_DQ[42] DDR2_DQ[43] DDR2_DQ[44] DDR2_DQ[45] DDR2_DQ[46] DDR2_DQ[47] DDR2_DQ[48] DDR2_DQ[49] DDR2_DQ[5] DDR2_DQ[50] DDR2_DQ[51] DDR2_DQ[52] DDR2_DQ[53] DDR2_DQ[54] DDR2_DQ[55] DDR2_DQ[56] DDR2_DQ[57] DDR2_DQ[58] DDR2_DQ[59] DDR2_DQ[6] DDR2_DQ[60] DDR2_DQ[61] DDR2_DQ[62] DDR2_DQ[63] DDR
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR2_DQS_DN[13] DDR2_DQS_DN[14] DDR2_DQS_DN[15] DDR2_DQS_DN[16] DDR2_DQS_DN[17] DDR2_DQS_DN[2] DDR2_DQS_DN[3] DDR2_DQS_DN[4] DDR2_DQS_DN[5] DDR2_DQS_DN[6] DDR2_DQS_DN[7] DDR2_DQS_DN[8] DDR2_DQS_DN[9] DDR2_DQS_DP[0] DDR2_DQS_DP[1] DDR2_DQS_DP[10] DDR2_DQS_DP[11] DDR2_DQS_DP[12] DDR2_DQS_DP[13] DDR2_DQS_DP[14] DDR2_DQS_DP[15] DDR2_DQS_DP[16] DDR2_DQS_DP[17] DDR2_DQS_DP[2] DDR2_DQS_DP[3] DDR2_DQS_DP[4] DDR2_DQS_DP[5] DDR2_DQS_DP[6] DDR2_DQS_DP
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR2_MA[14] DDR2_MA[15] DDR2_MA[16] DDR2_MA[17] DDR2_MA[2] DDR2_MA[3] DDR2_MA[4] DDR2_MA[5] DDR2_MA[6] DDR2_MA[7] DDR2_MA[8] DDR2_MA[9] DDR2_ODT[0] DDR2_ODT[1] DDR2_ODT[2] DDR2_ODT[3] DDR2_ODT[4] DDR2_ODT[5] DDR2_PAR DDR23_VREF DDR3_ACT_N DDR3_ALERT_N Y14 R13 P14 T14 T18 L17 R19 P18 M18 U19 L19 P20 Y16 W15 R15 AB14 AE17 AD14 R17 T40 L21 M22 G13 K14 J21 G21 J11 F22 E21 A21 D22 B22 K22 C17 D20 D18 C19 A17 B20 B18 A19 B16 C15 F10 H10 SSTL SS
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR3_CS_N[4] DDR3_CS_N[5] DDR3_CS_N[6]/CID[3] DDR3_CS_N[7]/CID[4] DDR3_CS_N[8] DDR3_CS_N[9] DDR3_DQ[0] DDR3_DQ[1] DDR3_DQ[10] DDR3_DQ[11] DDR3_DQ[12] DDR3_DQ[13] DDR3_DQ[14] DDR3_DQ[15] DDR3_DQ[16] DDR3_DQ[17] DDR3_DQ[18] DDR3_DQ[19] DDR3_DQ[2] DDR3_DQ[20] DDR3_DQ[21] DDR3_DQ[22] DDR3_DQ[23] DDR3_DQ[24] DDR3_DQ[25] DDR3_DQ[26] DDR3_DQ[27] DDR3_DQ[28] DDR3_DQ[29] DDR3_DQ[3] DDR3_DQ[30] DDR3_DQ[31] DDR3_DQ[32] DDR3_DQ[33] DDR3_DQ[34] DDR3_DQ[
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR3_DQ[44] DDR3_DQ[45] DDR3_DQ[46] DDR3_DQ[47] DDR3_DQ[48] DDR3_DQ[49] DDR3_DQ[5] DDR3_DQ[50] DDR3_DQ[51] DDR3_DQ[52] DDR3_DQ[53] DDR3_DQ[54] DDR3_DQ[55] DDR3_DQ[56] DDR3_DQ[57] DDR3_DQ[58] DDR3_DQ[59] DDR3_DQ[6] DDR3_DQ[60] DDR3_DQ[61] DDR3_DQ[62] DDR3_DQ[63] DDR3_DQ[7] DDR3_DQ[8] DDR3_DQ[9] DDR3_DQS_DN[0] DDR3_DQS_DN[1] DDR3_DQS_DN[10] DDR3_DQS_DN[11] DDR3_DQS_DN[12] DDR3_DQS_DN[13] DDR3_DQS_DN[14] DDR3_DQS_DN[15] DDR3_DQS_DN[16] DDR3_DQ
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR3_DQS_DP[10] DDR3_DQS_DP[11] DDR3_DQS_DP[12] DDR3_DQS_DP[13] DDR3_DQS_DP[14] DDR3_DQS_DP[15] DDR3_DQS_DP[16] DDR3_DQS_DP[17] DDR3_DQS_DP[2] DDR3_DQS_DP[3] DDR3_DQS_DP[4] DDR3_DQS_DP[5] DDR3_DQS_DP[6] DDR3_DQS_DP[7] DDR3_DQS_DP[8] C35 J33 F26 M4 B8 AH4 Y6 M26 M32 E25 H2 E7 AK2 AB4 L25 F38 L27 J27 L23 J23 K28 M28 M24 K24 G15 K16 L13 K20 M20 M12 K12 F12 J13 L11 F16 G17 J17 K18 F18 J19 G19 F20 D16 A13 D14 SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction DDR3_ODT[3] DDR3_ODT[4] DDR3_ODT[5] DDR3_PAR DEBUG_EN_N DMI_RX_DN[0] DMI_RX_DN[1] DMI_RX_DN[2] DMI_RX_DN[3] DMI_RX_DP[0] DMI_RX_DP[1] DMI_RX_DP[2] DMI_RX_DP[3] DMI_TX_DN[0] DMI_TX_DN[1] DMI_TX_DN[2] DMI_TX_DN[3] DMI_TX_DP[0] DMI_TX_DP[1] DMI_TX_DP[2] DMI_TX_DP[3] DRAM_PWR_OK_C01 DRAM_PWR_OK_C23 EAR_N ERROR_N[0] ERROR_N[1] ERROR_N[2] FIVR_FAULT FRMAGENT MEM_HOT_C01_N MEM_HOT_C23_N MSMI_N PE_HP_SCL PE_HP_SDA PE1A_RX_DN[0] PE1A_RX_DN[1] PE1A_R
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction PE1A_TX_DN[3] PE1A_TX_DP[0] PE1A_TX_DP[1] PE1A_TX_DP[2] PE1A_TX_DP[3] PE1B_RX_DN[4] PE1B_RX_DN[5] PE1B_RX_DN[6] PE1B_RX_DN[7] PE1B_RX_DP[4] PE1B_RX_DP[5] J45 K42 L43 K44 L45 J53 K54 J57 K56 L53 M54 L57 M56 H46 J47 H48 J49 K46 L47 K48 L49 L55 T54 T56 U55 N55 V54 V56 W55 AN49 AM50 AN51 AM52 AR49 AP50 AR51 AP52 AB54 AB56 AC55 AE57 AD54 AD56 AE55 AF58 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 P
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction PE2B_TX_DN[4] PE2B_TX_DN[5] PE2B_TX_DN[6] PE2B_TX_DN[7] PE2B_TX_DP[4] PE2B_TX_DP[5] PE2B_TX_DP[6] PE2B_TX_DP[7] PE2C_RX_DN[10] AG53 AH54 AN53 AP54 AJ53 AK54 AR53 AT54 AJ57 AR57 AH56 AK58 AL57 AU57 AK56 AM58 AY54 AW51 AV52 AW53 BB54 BA51 AY52 BA53 AT58 AP56 AY58 AY56 AV58 AT56 BA57 BB56 AV50 AW49 AV48 AW47 AY50 BA49 AY48 BA47 AF44 AG45 AF46 AA49 AH44 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction PE3A_RX_DP[1] PE3A_RX_DP[2] PE3A_RX_DP[3] PE3A_TX_DN[0] PE3A_TX_DN[1] PE3A_TX_DN[2] PE3A_TX_DN[3] PE3A_TX_DP[0] PE3A_TX_DP[1] PE3A_TX_DP[2] PE3A_TX_DP[3] PE3B_RX_DN[4] PE3B_RX_DN[5] PE3B_RX_DN[6] PE3B_RX_DN[7] PE3B_RX_DP[4] PE3B_RX_DP[5] PE3B_RX_DP[6] PE3B_RX_DP[7] PE3B_TX_DN[4] PE3B_TX_DN[5] PE3B_TX_DN[6] PE3B_TX_DN[7] PE3B_TX_DP[4] PE3B_TX_DP[5] PE3B_TX_DP[6] PE3B_TX_DP[7] PE3C_RX_DN[10] PE3C_RX_DN[11] PE3C_RX_DN[8] PE3C_RX_DN[9] PE3C_RX_
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction PE3D_RX_DN[14] PE3D_RX_DN[15] PE3D_RX_DP[12] PE3D_RX_DP[13] PE3D_RX_DP[14] PE3D_RX_DP[15] PE3D_TX_DN[12] PE3D_TX_DN[13] PE3D_TX_DN[14] AM46 AN45 AJ47 AR47 AP46 AR45 AA45 Y44 AC43 T44 AC45 AB44 AA43 P44 CG55 AV44 K52 CU49 CW49 AB48 BL51 AC41 BJ53 BM58 BK58 CF44 CD44 BG51 BF52 BN55 BP54 BN53 BP52 BR51 BP50 BR49 BJ49 BP48 BR47 BG53 BG55 BH56 BH54 BH50 BF58 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PC
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction QPI0_DRX_DN[8] QPI0_DRX_DN[9] QPI0_DRX_DP[0] QPI0_DRX_DP[1] QPI0_DRX_DP[10] QPI0_DRX_DP[11] QPI0_DRX_DP[12] QPI0_DRX_DP[13] QPI0_DRX_DP[14] QPI0_DRX_DP[15] QPI0_DRX_DP[16] QPI0_DRX_DP[17] QPI0_DRX_DP[18] QPI0_DRX_DP[19] QPI0_DRX_DP[2] QPI0_DRX_DP[3] QPI0_DRX_DP[4] QPI0_DRX_DP[5] QPI0_DRX_DP[6] QPI0_DRX_DP[7] QPI0_DRX_DP[8] QPI0_DRX_DP[9] QPI0_DTX_DN[0] QPI0_DTX_DN[1] QPI0_DTX_DN[10] QPI0_DTX_DN[11] QPI0_DTX_DN[12] QPI0_DTX_DN[13] QPI0_DTX_D
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction QPI0_DTX_DP[11] QPI0_DTX_DP[12] QPI0_DTX_DP[13] QPI0_DTX_DP[14] QPI0_DTX_DP[15] QPI0_DTX_DP[16] QPI0_DTX_DP[17] QPI0_DTX_DP[18] QPI0_DTX_DP[19] QPI0_DTX_DP[2] QPI0_DTX_DP[3] QPI0_DTX_DP[4] QPI0_DTX_DP[5] QPI0_DTX_DP[6] QPI0_DTX_DP[7] QPI0_DTX_DP[8] QPI0_DTX_DP[9] QPI1_CLKRX_DN QPI1_CLKRX_DP QPI1_CLKTX_DN QPI1_CLKTX_DP QPI1_DRX_DN[0] QPI1_DRX_DN[1] QPI1_DRX_DN[10] QPI1_DRX_DN[11] QPI1_DRX_DN[12] QPI1_DRX_DN[13] QPI1_DRX_DN[14] QPI1_DRX_DN[15
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction QPI1_DRX_DP[12] QPI1_DRX_DP[13] QPI1_DRX_DP[14] QPI1_DRX_DP[15] QPI1_DRX_DP[16] QPI1_DRX_DP[17] QPI1_DRX_DP[18] QPI1_DRX_DP[19] QPI1_DRX_DP[2] QPI1_DRX_DP[3] QPI1_DRX_DP[4] QPI1_DRX_DP[5] QPI1_DRX_DP[6] QPI1_DRX_DP[7] QPI1_DRX_DP[8] QPI1_DRX_DP[9] QPI1_DTX_DN[0] QPI1_DTX_DN[1] QPI1_DTX_DN[10] QPI1_DTX_DN[11] QPI1_DTX_DN[12] QPI1_DTX_DN[13] QPI1_DTX_DN[14] QPI1_DTX_DN[15] QPI1_DTX_DN[16] QPI1_DTX_DN[17] QPI1_DTX_DN[18] QPI1_DTX_DN[19] QPI1_D
Appendix A: Pin List Pin Name Pin Number Buffer Type Direction QPI1_DTX_DP[17] QPI1_DTX_DP[18] QPI1_DTX_DP[19] QPI1_DTX_DP[2] QPI1_DTX_DP[3] QPI1_DTX_DP[4] QPI1_DTX_DP[5] QPI1_DTX_DP[6] QPI1_DTX_DP[7] QPI1_DTX_DP[8] QPI1_DTX_DP[9] RESET_N RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD CT48 CT46 CT44 CU41 DC43 DD44 CT42 DC45 DD46 CU43 DC47 CR43 CF40 CP40 R41 M40 AV46 N41 CU51 CW51 B54 F
Appendix A: Pin List Pin Name Pin Number RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD BF44 BT44 CA43 BV44 BY44 DE53 C53 F56 D56 K58 H58 AU55 AR55 DE55 DD54 CY58 DA57 BP46 BM46 DC3 CY56 R53 U53 CT50 DA11 BL47 CA53 AM54 AP48 AE45 AA41 Y54 W41 V42 R43 P42 J41 H56 G43 F46 E53 BF48 C41 BH48 AM44 September 2014 Order No: 330783-001
Appendix A: Pin List Pin Name Pin Number RSVD RSVD SAFE_MODE_BOOT CN43 CL43 BK56 BU49 CP52 CC53 AN43 AU43 AR43 CA45 CF42 CG41 DB2 DB4 D2 C3 BA55 BJ47 BY46 CV50 AH52 AF52 CB16 CB18 CB20 CB22 CB24 CB26 CG17 CG19 CG21 CG23 CG25 CM16 CM18 CM20 CM22 CM24 CM26 CU17 CU19 CU21 CU23 CU25 DB16 SKTOCC_N SOCKET_ID[0] SOCKET_ID[1] SVIDALERT_N SVIDCLK SVIDDATA TCK TDI TDO TEST[0] TEST[1] TEST[2] TEST[3] TEST[4] THERMTRIP_N TMS TRST_N TXT_AGENT TXT_PLTEN VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01
Appendix A: Pin List Pin Name Pin Number Buffer Type VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN DB18 DB20 DB22 DB24 DB26 DE17 AC15 AC17 AC19 AC21 C11 C13 C21 E15 E17 E19 H12 H14 H16 H18 H20 H22 N11 N13 N15 N17 N19
Appendix A: Pin List Pin Name Pin Number Buffer Type VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN AN11 AN17 AP10 AP12 AP14 AP16 AP2 AP4 AP6 AP8 AR1 AR11 AR13 AR15 AR17 AR3 AR5 AR7 AR9 AT10 AT12 AT14 AT16 AT2 AT4 AT42 AT6 AT8 AU1 AU11 AU13 AU15 AU17 AU3 AU5 AU7 AU9 AV10 AV12 AV14 AV16 AV2 AV4 AV6 AV8 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR VCCIN VCCIN VCC
Appendix A: Pin List Pin Name Pin Number Buffer Type VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN AW1 AY42 BA1 BA11 BA13 BA15 BA17 BA3 BA5 BA7 BA9 BB10 BB12 BB14 BB16 BB2 BB4 BB6 BB8 BC1 BC11 BC13 BC15 BC17 BC3 BC5 BC7 BC9 BD10 BD12 BD14 BD16 BD2 BD4 BD42 BD6 BD8 BE1 BE11 BE13 BE15 BE17 BE3 BE5 BE7 PWR PWR PWR PWR PWR PWR
Appendix A: Pin List Pin Name Pin Number Buffer Type VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN BE9 BG1 BH10 BH12 BH14 BH16 BH2 BH4 BH42 BH6 BH8 BJ1 BJ11 BJ13 BJ15 BJ17 BJ3 BJ5 BJ7 BJ9 BK10 BK12 BK14 BK16 BK2 BK4 BK6 BK8 BL1 BL11 BL13 BL15 BL17 BL3 BL5 BL7 BL9 BM10 BM12 BM14 BM16
Appendix A: Pin List Pin Name Pin Number Buffer Type VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN VCCIN_SENSE VCCIO_IN VCCPECI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS BM8 BN11 BN13 BN15 BN17 BN3 BN5 BN7 BN9 BP10 BP16 BP42 BR17 BU17 BV42 BY18 BY20 BY22 BY24 BY26 BY30 BY34 BY36 BY38 BY40 BY42 BN1 CC41 CD42 A23 A37 A39 A41 A43 A45 A47 A49 A5 A51 A7 AA25 AA29 AA3 AA31 AA39
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AA55 AA7 AB12 AB36 AB40 AB42 AC11 AC29 AC7 AC9 AD10 AD12 AD36 AD4 AD40 AD42 AD44 AD46 AD48 AD50 AD52 AD6 AD8 AE13 AE15 AE19 AE23 AE27 AE29 AE33 AE35 AE39 AE41 AE43 AE47 AE49 AE51 AE53 AF10 AF16 AF18 AF2 AF20 AF22 AF24 GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS AF26 AF28 AF30 AF32 AF34 AF36 AF38 AF4 AF40 AF54 AF56 AF6 AF8 AG11 AG13 AG17 AG19 AG21 AG25 AG31 AG37 AG43 AG55 AG57 AH14 AH2 AH58 AH6 AJ11 AJ17 AK16 AK4 AK42 AK44 AK46 AK48 AK50 AK52 AK6 AL11 AL43 AL45 AL47 AL49 AL51 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS VSS VSS VSS VSS VSS VSS VSS VSS VS
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AL53 AM10 AM12 AM14 AM16 AM2 AM4 AM56 AM6 AM8 AN1 AN13 AN15 AN3 AN5 AN55 AN57 AN7 AN9 AP42 AP44 AP58 AT44 AT46 AT48 AT50 AT52 AU45 AU47 AU49 AU51 AU53 AV42 AV54 AV56 AW11 AW13 AW15 AW17 AW3 AW5 AW55 AW57 AW7 AW9 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS VSS
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AY10 AY12 AY14 AY16 AY2 AY4 AY44 AY6 AY8 B10 B36 B40 B52 B6 BB42 BB46 BB50 BB58 BC45 BC47 BC49 BC51 BC53 BC55 BC57 BD52 BD54 BD56 BE49 BE51 BF10 BF12 BF14 BF16 BF2 BF4 BF42 BF6 BF8 BG11 BG13 BG15 BG17 BG3 BG45 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS VSS VSS VSS VSS VS
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS BG47 BG5 BG7 BG9 BH58 BJ55 BJ57 BK42 BK46 BK48 BK50 BK52 BK54 BL45 BL49 BL57 BN43 BN57 BP12 BP14 BP4 BP58 BP6 BP8 BR1 BR11 BR13 BR15 BR3 BR5 BR53 BR55 BR57 BR7 BR9 BT10 BT16 BT42 BT46 BT48 BT50 BT52 BT54 BT56 BU3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS BU45 BU47 BU5 BU51 BV10 BV16 BW15 BW17 BW43 BW5 BW7 BY10 BY28 BY32 BY58 BY8 C33 C5 C55 CA13 CA15 CA17 CA19 CA21 CA23 CA25 CA27 CA29 CA31 CA33 CA35 CA37 CA39 CA41 CA5 CA55 CA57 CB10 CB12 CB14 CB2 CB30 CB34 CB36 CB38 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GN
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CB40 CB42 CB44 CB46 CB48 CB50 CB52 CB54 CB56 CC11 CC3 CC33 CC43 CC45 CC47 CC49 CC5 CC7 CC9 CD12 CD4 CD40 CD6 CD8 CE15 CE33 CE43 CE45 CE7 CF10 CF12 CF28 CF32 CG27 CG29 CG31 CG33 CG35 CG37 CG39 CG43 CG45 CG5 CG53 CG7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GN
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CH12 CH30 CH34 CH36 CH38 CH40 CH42 CH44 CH46 CH48 CH50 CH52 CH54 CH56 CJ15 CJ3 CJ33 CJ41 CJ43 CJ45 CJ47 CJ49 CJ51 CJ7 CK12 CK4 CK40 CK52 CK54 CL11 CL15 CL7 CL9 CM10 CM28 CM32 CM40 CM52 CM54 CM6 CM8 CN11 CN13 CN27 CN29 GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CN3 CN31 CN33 CN35 CN37 CN39 CN5 CN53 CN55 CN57 CN7 CP12 CP14 CP30 CP34 CP36 CP38 CP4 CP42 CP44 CP46 CP48 CP50 CP56 CR33 CR41 CR45 CR47 CR49 CR7 CR9 CT12 CT2 CT40 CU1 CU15 CU33 CU7 CV12 CV28 CV32 CV40 CV54 CV58 CV6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GN
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CW1 CW15 CW27 CW29 CW31 CW33 CW35 CW37 CW39 CW5 CW53 CW55 CW57 CW7 CY10 CY12 CY2 CY30 CY34 CY36 CY38 CY4 CY42 CY44 CY46 CY48 CY50 CY52 CY8 D10 D24 D36 D4 D40 DA27 DA3 DA35 DA41 DA43 DA45 DA47 DA49 DA51 DA53 DA55 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND G
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DA9 DB12 DB34 DB40 DB58 DB6 DC5 DC53 DC55 DD10 DD12 DD34 DD38 DD40 DD6 DE15 DE35 DE7 DF12 DF40 DF42 DF44 DF46 DF48 DF50 DF52 DF8 E1 E3 E39 E41 F2 F30 F32 F36 F4 F42 F44 F48 F50 G1 G23 G27 G33 G35 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND G
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS G39 G41 G45 G47 G49 G5 G51 G53 G57 G9 H24 H26 H28 H30 H32 H34 H36 H40 H54 H6 H8 J25 J29 J3 J31 J37 J5 J55 J7 K10 K36 K40 L29 L39 L41 L5 M10 M2 M36 M42 M44 M46 M48 M50 M52 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GN
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS N23 N27 N29 N33 N35 N37 N39 N43 N45 N47 N49 N5 N51 N53 P10 P24 P26 P28 P30 P32 P34 P38 P40 P54 P56 R11 R25 R29 R31 R39 R5 R55 R9 T36 T4 T42 T6 T8 U29 U3 U39 U41 U43 U7 V10 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND G
Appendix A: Pin List Pin Name Pin Number Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_VCCIN_SENSE V12 V36 V44 V46 V48 V50 V52 W23 W27 W33 W35 W39 W43 W45 W47 W49 W51 W53 W7 Y12 Y24 Y26 Y28 Y30 Y32 Y34 Y36 Y4 Y42 Y56 BP2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND September 2014 Order No: 330783-001 Direction Intel(R) Xeon(R) Processor
