Specification Sheet

Intel

Xeon

Processor E5-1600/E5-2600/E5-4600 v2 Product Families 61

Datasheet Volume One of Two

Interfaces

2.5.2.6.29 ACPI P-T Notify Write & Read

This feature enables the processor turbo capabili

ty when used in conjunction with the

PECI package RAPL or power limit. When the BMC sets the package power limit to a

value below TDP, it also determines a new corresponding turbo frequency and notifies

the OS using the ‘ACPI Notify’ mechanism as supported by the _PPC or performance

present capabilities object. The BMC then notifies the processor PCU using the PECI

‘ACPI P-T Notify’ service by programming a new state that is one p-state below the

turbo frequency sent to the OS via the _PPC method.

When the OS requests a p-state higher than what is specified in bits [7:0] of the PECI

ACPI P-T Notify data field, the CPU will treat it as request for P0 or turbo. The PCU will

use the IA32_ENERGY_PERFORMANCE_BIAS register settings to determine the exact

extent of turbo. Any OS p-state request that is equal to or below what is specified in

the PECI ACPI P-T Notify will be granted as long as the RAPL power limit does not

impose a lower p-state. However, turbo will not be enabled in this instance even if there

is headroom between the processor energy consumption and the RAPL power limit.

This feature does not affect the Thermal Monitor behavior of the processor nor is it

impacted by the setting of the power limit clamp mode bit.

2.5.2.6.30 Caching Agent TOR Read

This feature allows the PECI host to read the Caching Agent (Cbo) Table of Requests

OR).

This information is useful for debug in the event of a 3-strike timeout that

results in a processor IERR assertion. The 16-bit parameter field is used to specify the

Cbo index, TOR array index and bank number according to the following bit

assignments.

• Bits [1:0] - Bank Number - legal values from 0 to 2

• Bits [6:2] - TOR Array Index - legal values from 0 to 19

• Bits [10:7] - Cbo Index - legal values from 0 to 7

• Bit [11] - Read Mode - should be set to ‘0’ for TOR

reads, ‘1’ for Core ID reads

• Bits [15:12] - Reserved

Bit[11] is the Read Mode bit and should be set to ‘0’ for TOR reads. The Read Mode bit

can alternatively be set to ‘1’ to read the ‘Core ID’ (with associated valid bit as shown in

Figure 2-40) that points to the first core that asserted the IERR. In this case bits [10:0]

of the parameter field are ignored. The ‘Core ID’ read may not return valid data until at

least 1 mS after the IERR assertion.

Figure 2-39. ACPI P-T Notify Data

ACPI P-T Notify Data

New P1 stateReserved