Specification Sheet

Interfaces
42 Intel
®
Xeon
®
Processor E5-1600/E5-2600/E5-4600 v2 Product Families
Datasheet Volume One of Two
Notes:
1. Time, energy and power units should be assumed, where applicable, to be based on values returned by a read of the
PACKAGE_POWER_SKU_UNIT MSR or through the Package Power SKU Unit PCS read service.
2.5.2.6.2 DRAM Thermal Estimation Configuration Data Read/Write
This feature is relevant only when activity
-based DRAM temperature estimation
methods are being utilized and would apply to all the DIMMs on all the memory
channels. The write allows the PECI host to configure the ‘β’ and ‘θ’ variables in
Figure 2-12 for DRAM channel temperature filtering as per the equation below:
T
N
= β ∗ T
N
-1 + θ ∗ ΔEnergy
T
N
and T
N-1
are the current and previous DRAM temperature estimates respectively in
degrees Celsius, ‘β’ is the DRAM temperature decay factor, ‘ΔEnergy’ is the energy
difference between the current and previous memory transactions as determined by
the processor power control unit and ‘θ’ is the DRAM energy-to-temperature translation
coefficient. The default value of ‘β’ is 0x3FF. ‘θ’ is defined by the equation:
θ = (1 - β) ∗ (Thermal Resistance) ∗ (Scaling Factor)
The ‘Thermal Resistance’ serves as a multiplier for translation of DRAM energy changes
to corresponding temperature changes and may be derived from actual platform
characterization data. The ‘Scaling Factor’ is used to convert memory transaction
information to energy units in Joules and can be derived from system/memory
configuration information. Refer to the Intel® 64 and IA-32 Architectures Software
Developer’s Manual for methods to program and access ‘Scaling Factor’ information.
DRAM Power
Limit Data
Write / Read
34
0x0000
N/A DRAM Plane
Power Limit Data
Write DRAM
Power Limit
Data
MSR 618h:
DRAM_POWER_LIMIT
CSR:
DRAM_PLANE_POWER_LIMIT
DRAM Power
Limit Data
Write / Read
34
0x0000
DRAM Plane Power
Limit Data
N/A Read DRAM
Power Limit
Data
MSR 618h:
DRAM_POWER_LIMIT
CSR:
DRAM_PLANE_POWER_LIMIT
DRAM Power
Limit
Performance
Status Read
38
0x0000
Accumulated DRAM
throttle time
N/A Read sum of all
time durations
for which each
DIMM has been
throttled
CSR:
DRAM_RAPL_PERF_STATUS
Table 2-6. RdPkgConfig() & WrPkgConfig() DRAM Thermal and Power Optimization
Services Summary (Sheet 2 of 2)
Service
Index
Value
(decimal)
Parameter
Value
(word)
RdPkgConfig()
Data
(dword)
WrPkgConfig()
Data
(dword)
Description
Alternate
Inband
MSR or CSR
Access
Figure 2-12. DRAM Thermal Estimation Configuration Data
Memory Thermal Estimation Configuration Data
RESERVED
1031
BETA VARIABLE
9 0
THETA VARIABLE
1920