Specification Sheet

Overview
16 Intel
®
Xeon
®
Processor E5-1600/E5-2600/E5-4600 v2 Product Families
Datasheet Volume One of Two
Overview
16
1.1.1 Processor Feature Details
• Up to 12 execution cores
• Each core supports two threads (Intel
®
Hyper-Threading Technology), up to 24
threads per socket
• 46-bit physical addressing and 48-bit virtual addressing
• 1 GB large page support for server applications
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data mid-level (L2) cache for each core
•Up to 30 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level
cache (LLC),
shared among all cores
• The Intel® Xeon® processor E5-2600 v2 and E5-4600 v2 product families supports
Directory Mode, Route Through, and Node IDs to reduce unnecessary Intel
®
QuickPath Interconnect traffic by tracking cache lines present in remote sockets.
• Protected Processor Inventory Number (PPIN): A solution for inventory
management available on Intel
®
Xeon Processor E5-2600 v2 product families for
use in server platforms. This feature is not supported on E5-2600 Workstation
models.
1.1.2 Supported Technologies
•Intel
®
Virtualization Technology (Intel
®
VT)
•Intel
®
Virtualization Technology for Directed I/O (Intel
®
VT-d)
• APIC Virtualization (APICv)
•Intel
®
Virtualization Technology Processor Extensions
•Intel
®
Trusted Execution Technology (Intel
®
TXT)
•Intel
®
64 Architecture
•Intel
®
Streaming SIMD Extensions 4.1 (Intel
®
SSE4.1)
•Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
•Intel
®
Advanced Vector Extensions (Intel
®
AVX)
•Intel
®
AVX Floating Point Bit Depth Conversion (Float 16)
•Intel
®
Hyper-Threading Technology
• Execute Disable Bit
•Intel
®
Turbo Boost Technology
•Intel
®
Intelligent Power Technology
• Enhanced Intel SpeedStep® Technology
•Intel
®
Dynamic Power Technology (Memory Power Management)
•Intel
®
Secure Key, formerly known as Digital Random Number Generator (DRNG)
•Intel
®
OS Guard, formerly known as Supervisor Mode Execution Protection
Bit (SMEP)