Specification Sheet

Thermal Management Specifications

120 Intel

Xeon

Processor E5-1600/E5-2600/E5-4600 v2 Product Families

Datasheet Volume One of Two

are programmable via TEMP_OEM_HI, TEMP_LOW, TEMP_MID, and TEMP_HI

threshold settings in the iMC. In Level mode, when asserted, the signal indicates to

the platform that a BIOS-configured thermal threshold has been reached by one or

more DIMMs in the covered channel pair.

5.2.6.4 Integrated Dual SMBus Master Controllers for System Memory

Interface

The processor includes two integrated SMBus master controllers running at 100 KHz for

dedicated PCU access to the serial presence detect (SPD) devices and thermal sensors

(TSoD) on the DIMMs. Each controller is responsible for a pair of memory channels and

supports up to eight SMBus slave devices. Note that clock-low stretching is not

supported by the processor. To avoid design complexity and minimize package C-state

transitions, the SMBus interface between the processor and DIMMs must be connected.

The SMBus controllers for the system memory interface support the following SMBus

protocols/commands:

• Random byte Read

•Byte Write

•I

C* Write to Pointer Register

•I

C Present Pointer Register Word Read

•I

C Pointer Write Register Read.

Refer to the

System Management Bus (SMBus) Specification, Revision 2.0 for standing

timing protocols and specific command structure details.