Datasheet

Processor Integrated I/O (IIO) Configuration Registers
92 Datasheet, Volume 2
3.4 Integrated I/O Core Registers (Device 8, Function
0-3)
This section describes the standard PCI configuration registers and device specific
Configuration Registers related to below:
• Intel VT-d, address mapping, system management — Device 8, Function 0
• Semaphore and Scratchpad — Device 8, Function 1
• System control/status — Device 8, Function 2
• Miscellaneous Registers — Device 8, Function 3
3.4.1 Configuration Register Map (Device 8, Function 0-3)
Table 3-7. Core Registers (Device 8, Function 0) — Offset 000h–0FFh
DID VID 00h 80h
PCISTS PCICMD 04h
84h
CCR RID 08h
88h
HDR CLSR 0Ch 8Ch
10h 90h
14h 94h
18h IIOMISCCTRL 98h
1Ch IIOMISCSS 9Ch
20h A0h
24h A4h
28h TSEGCTRL A8h
SID SVID 2Ch ACh
30h B0h
CAPPTR
1
Notes:
1. CAPPTR points to the first capability block.
34h
B4h
38h B8h
INTPIN INTLIN 3Ch BCh
EXPCAP NXTPTR CAPID 40h
C0h
DEVCAP 44h
C4h
DEVSTS DEVCTRL 48h
C8h
RESERVEDPCI Express Header space
4Ch
CCh
50h TOLM D0h
54h
TOHM
D4h
58h D8h
5Ch
NCMEM.BASE
DCh
60h E0h
64h
NCMEM.LIMIT
E4h
68h E8h
6Ch
ECh
70h DEVHIDE 1 F0h
74h
F4h
78h DEVHIDE 2 F8h
7Ch FCh