Datasheet

Datasheet, Volume 2 9
4.9.9 MC_TEST_PAT_IS................................................................................. 235
4.9.10 MC_TEST_PAT_DCD ............................................................................. 235
4.9.11 MC_TEST_EP_SCCTL............................................................................. 236
4.9.12 MC_TEST_EP_SCD................................................................................ 236
4.10 Integrated Memory Controller Channel Control Registers ...................................... 237
4.10.1 MC_CHANNEL_0_DIMM_RESET_CMD
MC_CHANNEL_1_DIMM_RESET_CMD ...................................................... 237
4.10.2 MC_CHANNEL_0_DIMM_INIT_CMD
MC_CHANNEL_1_DIMM_INIT_CMD......................................................... 238
4.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS
MC_CHANNEL_1_DIMM_INIT_PARAMS.................................................... 239
4.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS
MC_CHANNEL_1_DIMM_INIT_STATUS .................................................... 240
4.10.5 MC_CHANNEL_0_DDR3CMD
MC_CHANNEL_1_DDR3CMD................................................................... 241
4.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT..................................... 242
4.10.7 MC_CHANNEL_0_MRS_VALUE_0_1
MC_CHANNEL_1_MRS_VALUE_0_1......................................................... 242
4.10.8 MC_CHANNEL_0_MRS_VALUE_2
MC_CHANNEL_1_MRS_VALUE_2 ............................................................ 243
4.10.9 MC_CHANNEL_0_RANK_PRESENT
MC_CHANNEL_1_RANK_PRESENT........................................................... 244
4.10.10MC_CHANNEL_0_RANK_TIMING_A
MC_CHANNEL_1_RANK_TIMING_A ......................................................... 245
4.10.11MC_CHANNEL_0_RANK_TIMING_B
MC_CHANNEL_1_RANK_TIMING_B ......................................................... 247
4.10.12MC_CHANNEL_0_BANK_TIMING
MC_CHANNEL_1_BANK_TIMING............................................................. 248
4.10.13MC_CHANNEL_0_REFRESH_TIMING
MC_CHANNEL_1_REFRESH_TIMING........................................................ 248
4.10.14MC_CHANNEL_0_CKE_TIMING
MC_CHANNEL_1_CKE_TIMING............................................................... 249
4.10.15MC_CHANNEL_0_ZQ_TIMING
MC_CHANNEL_1_ZQ_TIMING................................................................. 250
4.10.16MC_CHANNEL_0_RCOMP_PARAMS
MC_CHANNEL_1_RCOMP_PARAMS.......................................................... 250
4.10.17MC_CHANNEL_0_ODT_PARAMS1
MC_CHANNEL_1_ODT_PARAMS1............................................................ 251
4.10.18MC_CHANNEL_0_ODT_PARAMS2
MC_CHANNEL_1_ODT_PARAMS2............................................................ 252
4.10.19MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD
MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD........................................ 252
4.10.20MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD
MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD........................................ 253
4.10.21MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR
MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR ....................................... 253
4.10.22MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR
MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR ....................................... 253
4.10.23MC_CHANNEL_0_WAQ_PARAMS
MC_CHANNEL_1_WAQ_PARAMS............................................................. 254
4.10.24MC_CHANNEL_0_SCHEDULER_PARAMS
MC_CHANNEL_1_SCHEDULER_PARAMS................................................... 255
4.10.25MC_CHANNEL_0_MAINTENANCE_OPS
MC_CHANNEL_1_MAINTENANCE_OPS..................................................... 255
4.10.26MC_CHANNEL_0_TX_BG_SETTINGS
MC_CHANNEL_1_TX_BG_SETTINGS........................................................ 256
4.10.27MC_CHANNEL_0_RX_BGF_SETTINGS
MC_CHANNEL_1_RX_BGF_SETTINGS...................................................... 257