Datasheet

Processor Integrated I/O (IIO) Configuration Registers
86 Datasheet, Volume 2
3.3.6.3 DMIVCCAP2—DMI Port VC Capability Register 2
This register Describes the configuration of PCI Express Virtual Channels associated
with this port.
3.3.6.4 DMIVCCTL—DMI Port VC Control
BAR: DMIRCBAR
Register: DMIVCCAP2
Offset: 0008h
Bit Attr Default Description
31:24 RO 0h Reserved for VC Arbitration Table Offset
23:8 RO 0h Reserved
7:0 RO 0h Reserved for VC Arbitration Capability (VCAC)
BAR: DMIRCBAR
Register: DMIVCCTL
Offset: 000Ch
Bit Attr Default Description
15:4 RO 0h Reserved
3:1 RW 0h
VC Arbitration Select (VCAS)
This field will be programmed by software to the only possible value as
indicated in the VC Arbitration Capability field.
The value 000b when written to this field will indicate the VC arbitration
scheme is hardware fixed (in the root complex). This field cannot be modified
when more than one VC in the LPVC group is enabled.
000 = Hardware fixed arbitration scheme, for example, Round Robin
Others = Reserved
Refer to the latest PCI Express Base Specification for more details.
0RO 0hReserved for Load VC Arbitration Table